From nobody Sun Feb 8 01:12:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15DB5C433FE for ; Thu, 24 Nov 2022 08:43:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229899AbiKXInP (ORCPT ); Thu, 24 Nov 2022 03:43:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229599AbiKXInN (ORCPT ); Thu, 24 Nov 2022 03:43:13 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 277DC72982 for ; Thu, 24 Nov 2022 00:42:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669279336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9oc/CybFzgvV8B8FFM+ex66MR6wvz6dieP3wlzbGgsM=; b=hnVDSPhrQrbb21oQZKyLQ0Gil3XP81LcVM8sdwZ6dK1xQZDvg09kI17KSnXw/CtgmqBY33 2Q4yXtuZMhgQKu3ZquE+JwAWcoM6NMNGEeaUU78FUSVwdnUh2std8ri2Jt0VF2whw4EAig O4SFfS71jebNNs3EE8rPf5FdtOnxb4EXkiGuOSes1HIxuXAl0lHYIZWh7HLxrWCWQoy+T5 Gfx/V1+WOr7cpSZrlqW2dtnhFJWns7mseddayYONnjw0UXXkeF2oqB2izYIojIIV19sc6h 0AyLDHS3YzXQWQHxPgdYquItJYuCEYSP5H3vMxonhpNMuZkzIwCim+NL3WXr/w== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-224-Cmjdxds4MA606ZxQugMShw-1; Thu, 24 Nov 2022 03:42:15 -0500 X-MC-Unique: Cmjdxds4MA606ZxQugMShw-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Thu, 24 Nov 2022 00:42:09 -0800 From: Rahul Tanwar To: Rahul Tanwar , Andy Shevchenko , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , Subject: [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Date: Thu, 24 Nov 2022 16:41:40 +0800 Message-ID: <20221124084143.21841-2-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com> References: <20221124084143.21841-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel's APIC family of interrupt controllers support local APIC (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic & ioapic from text to YAML schema. Separate lapic & ioapic schemas. Addditionally, add description which was missing in text file and add few more required standard properties which were also missing in text file. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar Reviewed-by: Rob Herring --- .../intel,ce4100-ioapic.txt | 26 -------- .../intel,ce4100-ioapic.yaml | 60 +++++++++++++++++++ .../intel,ce4100-lapic.yaml | 57 ++++++++++++++++++ 3 files changed, 117 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-lapic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-i= oapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible =3D "intel,ce4100-ioapic"; - #interrupt-cells =3D <2>; - - Device's interrupt property: - - interrupts =3D

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible =3D "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.yaml new file mode 100644 index 000000000000..39ab8cdd19b4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-i= oapic.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioap= ic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) + +maintainers: + - Rahul Tanwar + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for I/O APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-ioapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + ioapic1: interrupt-controller@fec00000 { + compatible =3D "intel,ce4100-ioapic"; + reg =3D <0xfec00000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-lapic.yaml new file mode 100644 index 000000000000..55184cb49432 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapi= c.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) + +maintainers: + - Rahul Tanwar + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for local APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-lapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + lapic0: interrupt-controller@fee00000 { + compatible =3D "intel,ce4100-lapic"; + reg =3D <0xfee00000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; --=20 2.17.1 From nobody Sun Feb 8 01:12:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CDB0C4332F for ; Thu, 24 Nov 2022 08:43:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230071AbiKXIn1 (ORCPT ); Thu, 24 Nov 2022 03:43:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229962AbiKXInW (ORCPT ); Thu, 24 Nov 2022 03:43:22 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E37F179927 for ; Thu, 24 Nov 2022 00:42:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669279342; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bSWgzt8uUrAzN6dnc8c6kjh1UlFQHYngZsNHw6hiwAw=; b=ayVJ013rLLdav8u5bh6oBGagZBRJjUXvx8QdYrh4zxiRkt68YIozHZcQ5pwZkUUK18IzcN /g4U9f0jT86PBZt8boC2pNmfiTiO5ntd6KCvsloLe+mNOueRgLZOTTKQn++sbZwR6mcS8g clNbBdai1E6+IW62/mbRvl5lqqAWS0ZBabIAiYQkSxg4KzpgVZMlxbwfD4wyI0pEItAEwv B8llqSAE9eUWnAK7L0rZWUoE/+sLcLWimRTJv9yYeq2N7pJboQZk5RuGzMsnXWF/24/FHn ZoiBt+VxRaoEdAPNglaHduPFEk7KeYEp/lqijBIZv80jbsnsxhiW0fV+9QiE5g== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-316-Hfmy2PVaNgmf4o3uDeRJEg-1; Thu, 24 Nov 2022 03:42:20 -0500 X-MC-Unique: Hfmy2PVaNgmf4o3uDeRJEg-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Thu, 24 Nov 2022 00:42:15 -0800 From: Rahul Tanwar To: Rahul Tanwar , Andy Shevchenko , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , Subject: [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Date: Thu, 24 Nov 2022 16:41:41 +0800 Message-ID: <20221124084143.21841-3-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com> References: <20221124084143.21841-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar Reviewed-by: Rob Herring --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-lapic.yaml index 55184cb49432..d2d0145cb889 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml @@ -39,6 +39,19 @@ properties: '#interrupt-cells': const: 2 =20 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mod= e. + For ACPI or MPS spec compliant systems, it is figured out by some re= ad + only bit field/s available in their respective defined data structur= es. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt del= ivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -54,4 +67,5 @@ examples: reg =3D <0xfee00000 0x1000>; interrupt-controller; #interrupt-cells =3D <2>; + intel,virtual-wire-mode; }; --=20 2.17.1 From nobody Sun Feb 8 01:12:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70B73C4332F for ; Thu, 24 Nov 2022 08:43:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbiKXIna (ORCPT ); Thu, 24 Nov 2022 03:43:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229628AbiKXInZ (ORCPT ); Thu, 24 Nov 2022 03:43:25 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9C46D80 for ; Thu, 24 Nov 2022 00:42:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669279349; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AkBrFNa8JXU1rnG3IW0QD6QbjBzAOYoAULmyjQGwhog=; b=pxayFnwuIfFEMe13+NffWtMWNE+wX1XXb40o1mXhQ9Ouy/VHGXJqSGITgVwurM9J9QYN4E RwOy+oDJOi7FSn438APH6WP5/YSi6zQzylVC/KMst5W2G8RSm1xFUkZ73k7M9Knp5i3Zam 8kJ8RZdkGI+oPebG0TD5lBAuVC5wV1sC2mJgXFPmpD0LG94HCRSdV7iYEX2NMg85lgzTrp cAJg7Iy+pDASRk0Elrfafcf0mhJuX508uq0mhU1bzmUcKWtDiTHUQkYv/V1kFT8KfTyEJ5 dwz9dqvVoXmRL6rIFefHoc50X9H7KgHCUxLT3HgnJZh/G07v08AvdHu39+WtQg== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-594-ojRMO8yHPlqWmQuCPzaiqQ-1; Thu, 24 Nov 2022 03:42:27 -0500 X-MC-Unique: ojRMO8yHPlqWmQuCPzaiqQ-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Thu, 24 Nov 2022 00:42:22 -0800 From: Rahul Tanwar To: Rahul Tanwar , Andy Shevchenko , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , Subject: [PATCH v5 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Date: Thu, 24 Nov 2022 16:41:42 +0800 Message-ID: <20221124084143.21841-4-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com> References: <20221124084143.21841-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use latest available pr_lvl() instead of older printk(KERN_LVL) Just a upgrade of print utilities usage no functional changes. Reviewed-by: Andy Shevchenko Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5cd51f25f446..fcc6f1b7818f 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -248,7 +248,7 @@ static void __init dtb_add_ioapic(struct device_node *d= n) =20 ret =3D of_address_to_resource(dn, 0, &r); if (ret) { - printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); + pr_err("Can't obtain address from device node %pOF.\n", dn); return; } mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); @@ -265,7 +265,7 @@ static void __init dtb_ioapic_setup(void) of_ioapic =3D 1; return; } - printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); + pr_err("Error: No information about IO-APIC in OF.\n"); } #else static void __init dtb_ioapic_setup(void) {} --=20 2.17.1 From nobody Sun Feb 8 01:12:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42439C43219 for ; Thu, 24 Nov 2022 08:43:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230112AbiKXInn (ORCPT ); Thu, 24 Nov 2022 03:43:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230093AbiKXInf (ORCPT ); Thu, 24 Nov 2022 03:43:35 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C8E712AE2 for ; Thu, 24 Nov 2022 00:42:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669279353; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OKxjoXJRVhUevg2ny6svax9/xOJH1NA1wD73iH6x5No=; b=jlPE16zy1/+6oBXj2yf7Bj1h24mT5oZyQM7r+pEFIDRAqJ2U8kb4jjJXGejvoJVh7l6453 EOFy0JKUG3qc2WRL03hlPnC8sOMMrI9C4ZUY8q1OaLUyHVJxSKSVsr2H3gqdD+ehLBBObV Lyycte+SJB1Wf/atFHji+BCwoUs8+GBFAEeQ8zcHTBMfhvQ/lDjBflkZb0wTaNNePSmfZs Y4hsETFNN4Gc5j5QYV3q/2l4V7WIH5xvDCuxx4/lF5aDJYDDStB19Htw/5UAkbzs2QbJ74 p1V9guoVKfKstaGoJab3AXJcMC6CmK7amVI4k/wBMOkc2X3lta4uCKyBAKqtOA== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-140-D7sP0d26MK-eDxU0Y_y5qg-1; Thu, 24 Nov 2022 03:42:32 -0500 X-MC-Unique: D7sP0d26MK-eDxU0Y_y5qg-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Thu, 24 Nov 2022 00:42:27 -0800 From: Rahul Tanwar To: Rahul Tanwar , Andy Shevchenko , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , Subject: [PATCH v5 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Date: Thu, 24 Nov 2022 16:41:43 +0800 Message-ID: <20221124084143.21841-5-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com> References: <20221124084143.21841-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Presently, init/boot time interrupt delivery mode is enumerated only for ACPI enabled systems by parsing MADT table or for older systems by parsing MP table. But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This causes boot time crash for platforms which do not use 8259 compliant legacy PIC. Add support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. Reviewed-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index fcc6f1b7818f..458e43490414 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) return; } smp_found_config =3D 1; - pic_mode =3D 1; + if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { + pr_info("Virtual Wire compatibility mode.\n"); + pic_mode =3D 0; + } else { + pr_info("IMCR and PIC compatibility mode.\n"); + pic_mode =3D 1; + } + register_lapic_address(lapic_addr); } =20 --=20 2.17.1