From nobody Thu Apr 16 03:43:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EA7FC433FE for ; Wed, 23 Nov 2022 21:14:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237370AbiKWVOB (ORCPT ); Wed, 23 Nov 2022 16:14:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235462AbiKWVNs (ORCPT ); Wed, 23 Nov 2022 16:13:48 -0500 Received: from mail-qt1-x836.google.com (mail-qt1-x836.google.com [IPv6:2607:f8b0:4864:20::836]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CB452C65C for ; Wed, 23 Nov 2022 13:13:46 -0800 (PST) Received: by mail-qt1-x836.google.com with SMTP id fz10so26264qtb.3 for ; Wed, 23 Nov 2022 13:13:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=timesys-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iZJAARPx2SHtSQhuKCHJQqr1weKMEsXAzSQ/wjEgP/A=; b=2VLnkaozanxm/fqmdEy2NgJX+Vj307RM4OQqji23uaPYoksKrOM2UdlD19T40yFoll uoQJPjDBKAzXNPDhnl3i+7WhBNOCN7c4QrcQp1+L4y8PyVyqcHlUhxdfiWt8+037NBAv PTlPCRNXD45gQ4HNoQKAO/42mHAKfZiFa6Ifx9Kfc6bym0b/NRvTK8pORQbxn0Eo3pGu vNPrkxh880ysqwq2KaOsWZMcAABAaVjjmmK5lPLxmGwMx0JedI5gthVBfN8gvsGSNC+B eXCG1AN+EXggie2hc72e4AO9ykHncfZD/w2/z0SiZC3LXInA8jdcSjLlL9rLP1APjJCn 0hlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iZJAARPx2SHtSQhuKCHJQqr1weKMEsXAzSQ/wjEgP/A=; b=lYHOMphAITfPVDUW3J1y3MBbjOH9bE1rduaxN+MbUcHUfah8DN+H5mw4JLh7N9oyRN E3o+u059PkQRioGXoLMMIJZ6DCgs7LZSX9BggTB5GCbxmFG3rTQ7Vj8NzNlJ3MkveGou dWDXDuXRBfjQ0+20M2UvPytQCtiwj8jwNUDu04aGY3igzudQspSoa0J4tIqyA1Zddqls y6TZ6oJHlS90nA38qxk6OdjDcwY7Lay//ZkOiVS+kJM0Dhw9fSLjzVyOgJa3t8lCsK6T cn4BHVgJ+sMD1eWm01HmSFE32i8NdCj6UDNgpunMUwL8Ru0DuU20AEVzwCn1AfabanzT a4DQ== X-Gm-Message-State: ANoB5pmlNkrF11RMGb+CxJhPS6FTvO/dgUYtlRXYtMhbHdgZr6UqRHoF 10DdBVPg5Ah/4uJc+Q0MCcvVjQ== X-Google-Smtp-Source: AA0mqf6F0KbifRkIynWdRMtfuohUIrzqVZNQBhRwWVinUpmKtcemXQlxh/QyUTKv/ZPWIYVT1hpOIg== X-Received: by 2002:ac8:67c5:0:b0:3a4:f665:7791 with SMTP id r5-20020ac867c5000000b003a4f6657791mr28900709qtp.380.1669238025276; Wed, 23 Nov 2022 13:13:45 -0800 (PST) Received: from nathan-ideapad.. (d-75-76-18-234.oh.cpe.breezeline.net. [75.76.18.234]) by smtp.gmail.com with ESMTPSA id cf11-20020a05622a400b00b0039ee562799csm10222928qtb.59.2022.11.23.13.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:13:45 -0800 (PST) From: Nathan Barrett-Morrison Cc: nathan.morrison@timesys.com, greg.malysa@timesys.com, Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org (open list:SPI NOR SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/2] mtd: spi-nore: core: Add in framework for 8S-8S-8S Octal STR mode Date: Wed, 23 Nov 2022 16:13:34 -0500 Message-Id: <20221123211335.126417-2-nathan.morrison@timesys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221123211335.126417-1-nathan.morrison@timesys.com> References: <20221123211335.126417-1-nathan.morrison@timesys.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" While trying to bring up an Octal SPI device in STR mode, I found that there is currently no support for 8S-8S-8S. This patch adds the necessary, additional logic for doing so. Signed-off-by: Nathan Barrett-Morrison --- drivers/mtd/spi-nor/core.c | 57 ++++++++++++++++++++++++++++++++++++-- drivers/mtd/spi-nor/core.h | 5 +++- 2 files changed, 59 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index bee8fc4c9f07..66665c1bebd7 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2253,7 +2253,8 @@ static int spi_nor_set_addr_nbytes(struct spi_nor *no= r) { if (nor->params->addr_nbytes) { nor->addr_nbytes =3D nor->params->addr_nbytes; - } else if (nor->read_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { + } else if (nor->read_proto =3D=3D SNOR_PROTO_8_8_8_DTR || + nor->read_proto =3D=3D SNOR_PROTO_8_8_8) { /* * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So * in this protocol an odd addr_nbytes cannot be used because @@ -2335,7 +2336,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_no= r *nor) { struct spi_nor_flash_parameter *params =3D nor->params; struct spi_nor_erase_map *map =3D ¶ms->erase_map; - const u8 no_sfdp_flags =3D nor->info->no_sfdp_flags; + const u16 no_sfdp_flags =3D nor->info->no_sfdp_flags; u8 i, erase_mask; =20 if (no_sfdp_flags & SPI_NOR_DUAL_READ) { @@ -2359,6 +2360,13 @@ static void spi_nor_no_sfdp_init_params(struct spi_n= or *nor) SNOR_PROTO_1_1_8); } =20 + if (no_sfdp_flags & SPI_NOR_OCTAL_STR_READ) { + params->hwcaps.mask |=3D SNOR_HWCAPS_READ_8_8_8; + spi_nor_set_read_settings(¶ms->reads[SNOR_HWCAPS_READ_8_8_8], + 0, 20, SPINOR_OP_READ_FAST, + SNOR_PROTO_8_8_8); + } + if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) { params->hwcaps.mask |=3D SNOR_HWCAPS_READ_8_8_8_DTR; spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], @@ -2366,6 +2374,12 @@ static void spi_nor_no_sfdp_init_params(struct spi_n= or *nor) SNOR_PROTO_8_8_8_DTR); } =20 + if (no_sfdp_flags & SPI_NOR_OCTAL_STR_PP) { + params->hwcaps.mask |=3D SNOR_HWCAPS_PP_8_8_8; + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8], + SPINOR_OP_PP, SNOR_PROTO_8_8_8); + } + if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) { params->hwcaps.mask |=3D SNOR_HWCAPS_PP_8_8_8_DTR; /* @@ -2631,6 +2645,38 @@ static int spi_nor_init_params(struct spi_nor *nor) return 0; } =20 +/** spi_nor_octal_str_enable() - enable Octal STR I/O if needed + * @nor: pointer to a 'struct spi_nor' + * @enable: whether to enable or disable Octal STR + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_octal_str_enable(struct spi_nor *nor, bool enable) +{ + int ret; + + if (!nor->params->octal_str_enable) + return 0; + + if (!(nor->read_proto =3D=3D SNOR_PROTO_8_8_8 && + nor->write_proto =3D=3D SNOR_PROTO_8_8_8)) + return 0; + + if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) + return 0; + + ret =3D nor->params->octal_str_enable(nor, enable); + if (ret) + return ret; + + if (enable) + nor->reg_proto =3D SNOR_PROTO_8_8_8; + else + nor->reg_proto =3D SNOR_PROTO_1_1_1; + + return 0; +} + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @enable: whether to enable or disable Octal DTR @@ -2691,6 +2737,12 @@ static int spi_nor_init(struct spi_nor *nor) return err; } =20 + err =3D spi_nor_octal_str_enable(nor, true); + if (err) { + dev_dbg(nor->dev, "octal STR mode not supported\n"); + return err; + } + err =3D spi_nor_quad_enable(nor); if (err) { dev_dbg(nor->dev, "quad mode not supported\n"); @@ -2714,6 +2766,7 @@ static int spi_nor_init(struct spi_nor *nor) =20 if (nor->addr_nbytes =3D=3D 4 && nor->read_proto !=3D SNOR_PROTO_8_8_8_DTR && + nor->read_proto !=3D SNOR_PROTO_8_8_8 && !(nor->flags & SNOR_F_4B_OPCODES)) { /* * If the RESET# pin isn't hooked up properly, or the system diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 85b0cf254e97..56795db872c2 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -359,6 +359,7 @@ struct spi_nor_otp { * Table. * @otp: SPI NOR OTP info. * @octal_dtr_enable: enables SPI NOR octal DTR mode. + * @octal_str_enable: enables SPI NOR octal STR mode. * @quad_enable: enables SPI NOR quad mode. * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. * @convert_addr: converts an absolute address into something the flash @@ -508,7 +509,7 @@ struct flash_info { #define NO_CHIP_ERASE BIT(7) #define SPI_NOR_NO_FR BIT(8) =20 - u8 no_sfdp_flags; + u16 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) #define SECT_4K BIT(1) #define SPI_NOR_DUAL_READ BIT(3) @@ -516,6 +517,8 @@ struct flash_info { #define SPI_NOR_OCTAL_READ BIT(5) #define SPI_NOR_OCTAL_DTR_READ BIT(6) #define SPI_NOR_OCTAL_DTR_PP BIT(7) +#define SPI_NOR_OCTAL_STR_READ BIT(8) +#define SPI_NOR_OCTAL_STR_PP BIT(9) =20 u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0) --=20 2.30.2 From nobody Thu Apr 16 03:43:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 667D5C43219 for ; Wed, 23 Nov 2022 21:14:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236385AbiKWVOF (ORCPT ); Wed, 23 Nov 2022 16:14:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235580AbiKWVNs (ORCPT ); Wed, 23 Nov 2022 16:13:48 -0500 Received: from mail-qt1-x832.google.com (mail-qt1-x832.google.com [IPv6:2607:f8b0:4864:20::832]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6100360346 for ; Wed, 23 Nov 2022 13:13:47 -0800 (PST) Received: by mail-qt1-x832.google.com with SMTP id z6so20455qtv.5 for ; Wed, 23 Nov 2022 13:13:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=timesys-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=REepYSvQGyqEeu/ZRQp2JZIqxZIOwqWc5SzYerGHAew=; b=mculQF0leNtbQou2zemAjMCIPOe4mtbo6ZaI3SoQUOrPYbmpwZjKEURMJuNIddSc0K S0SKnprU6XhARUarT6G5oq5IhiYPe3iCfjHhP19NfZOCod6gSMVaM+N36/htjyEJDSCd 49SL3RXDf/lCk1srcNhPhPwOnmWmch4f72YD5UGOLHWQPMezBsZ7EZ+rngTEbpblm8IR Nn7+X0vSvW/en7Veg8K0fBQ4wt4jP+16DKieDVXvF1ZNlAokrCxrs0ZECvwXu4N6+Kb8 X9Ux96PTNRGle1f8x9TN2wF+3JIk4lWegfmhAovLg87swEFnBYR+at6lXd4wZWH2bEiX oRDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=REepYSvQGyqEeu/ZRQp2JZIqxZIOwqWc5SzYerGHAew=; b=ywlHDn9ZxBZfBmmvBgBslSwN3QDZrsVTk1o2lbSQSIQTK4/bhqriBxxoaWb4LiasKc qrxQxVZv7SH7TNDEPAs0hrNj0c+eL10uHox1AHHLqjVH0Lo1X7xvtwTkdlr9617nLRVL BrZh7cxUqr29A+UUDw4O98uJTagpne2X72jZ5u9w7y3Xk7CSyr4a2GZpdpsE1l/7MiCN SeV4wBXCCAE++loqQsoR4rmobCU4tPgk2IHqiYjh0xBnCUu1cjZa/zcISBQmVG7LJQxJ JSfsfGbOyZcmCSj0pWd0GJutgi63zLZwNv8IrMVZdtyfVFPZK1ZJEURC5EH9DWUo+LVJ 80Kg== X-Gm-Message-State: ANoB5plLvtZ2KesGwzwzu0V/edVM6aWF6S6Rn2+oOoXzZlFxyTRljIuC lTebsyGwSh6IQ5WQBGpR8btYCA== X-Google-Smtp-Source: AA0mqf6S8r1kTn9XVcCp36idhYyS6f+Vi9KZuRKjP5ZxGucP+Q+1FHhyCFZdkmIcqx9NZ68KJz2HpA== X-Received: by 2002:a05:622a:1184:b0:3a5:6f39:4bd7 with SMTP id m4-20020a05622a118400b003a56f394bd7mr9685697qtk.226.1669238026485; Wed, 23 Nov 2022 13:13:46 -0800 (PST) Received: from nathan-ideapad.. (d-75-76-18-234.oh.cpe.breezeline.net. [75.76.18.234]) by smtp.gmail.com with ESMTPSA id cf11-20020a05622a400b00b0039ee562799csm10222928qtb.59.2022.11.23.13.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:13:46 -0800 (PST) From: Nathan Barrett-Morrison Cc: nathan.morrison@timesys.com, greg.malysa@timesys.com, Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org (open list:SPI NOR SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/2] mtd: spi-nor: issi: Add in support for IS25LX256 chip, operating in Octal STR mode Date: Wed, 23 Nov 2022 16:13:35 -0500 Message-Id: <20221123211335.126417-3-nathan.morrison@timesys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221123211335.126417-1-nathan.morrison@timesys.com> References: <20221123211335.126417-1-nathan.morrison@timesys.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds the is25lx256 entry to the nor_parts table along with the additional STR enablement fixups and logic Signed-off-by: Nathan Barrett-Morrison --- drivers/mtd/spi-nor/issi.c | 101 +++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 89a66a19d754..89f3cdd51075 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -8,6 +8,15 @@ =20 #include "core.h" =20 +#define SPINOR_OP_STR_RD 0x8B /* Fast Read opcode in DTR mode */ +#define SPINOR_OP_STR_PP 0x82 /* Octal Input Fast Program */ +#define SPINOR_OP_RD_ANY_REG 0x85 /* Read volatile register */ +#define SPINOR_OP_WR_ANY_REG 0x81 /* Write volatile register */ +#define SPINOR_REG_CFR0V 0x00 /* For setting octal DTR mode */ +#define SPINOR_REG_CFR1V 0x01 /* For setting dummy cycles */ +#define SPINOR_OCT_STR 0xc7 /* Enable Octal DTR. */ +#define SPINOR_EXSPI 0xff /* Enable Extended SPI (default) */ + static int is25lp256_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -29,6 +38,94 @@ static const struct spi_nor_fixups is25lp256_fixups =3D { .post_bfpt =3D is25lp256_post_bfpt_fixups, }; =20 +static int spi_nor_issi_octal_str_enable(struct spi_nor *nor, bool enable) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + + if (enable) + *buf =3D SPINOR_OCT_STR; + else + *buf =3D SPINOR_EXSPI; + + op =3D (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), + SPI_MEM_OP_ADDR(enable ? 3 : 4, + SPINOR_REG_CFR0V, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, buf, 1)); + + if (!enable) + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_1_1_8); + else + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_1_1_1); + + + ret =3D spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + + /* Read flash ID to make sure the switch was successful. */ + op =3D (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), + buf, 1)); + + if (enable) + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_1_1_8); + else + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_1_1_1); + + + ret =3D spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; + + return 0; +} + +static void is25lx256_default_init(struct spi_nor *nor) +{ + nor->params->octal_str_enable =3D spi_nor_issi_octal_str_enable; +} + +static void is25lx256_post_sfdp_fixup(struct spi_nor *nor) +{ + /* Fixup read command to 8 dummy cycles, 1S-1S-8S */ + nor->params->hwcaps.mask |=3D SNOR_HWCAPS_READ_8_8_8; + spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8], + 0, 8, SPINOR_OP_STR_RD, + SNOR_PROTO_1_1_8); + + /* Fixup page program command to 1S-1S-8S */ + nor->params->hwcaps.mask |=3D SNOR_HWCAPS_PP_8_8_8; + spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8], + SPINOR_OP_STR_PP, SNOR_PROTO_1_1_8); + + /* + * The BFPT quad enable field is set to a reserved value so the quad + * enable function is ignored by spi_nor_parse_bfpt(). Make sure we + * disable it. + */ + nor->params->quad_enable =3D NULL; +} + +static struct spi_nor_fixups is25lx256_fixups =3D { + .default_init =3D is25lx256_default_init, + .post_sfdp =3D is25lx256_post_sfdp_fixup, +}; + static void pm25lv_nor_late_init(struct spi_nor *nor) { struct spi_nor_erase_map *map =3D &nor->params->erase_map; @@ -74,6 +171,10 @@ static const struct flash_info issi_nor_parts[] =3D { NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) .fixups =3D &is25lp256_fixups }, + { "is25lx256", INFO(0x9d5a19, 0, 128 * 1024, 256) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_STR_PP | SPI_NOR_OCTAL_STR_READ) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE) + .fixups =3D &is25lx256_fixups }, =20 /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2) --=20 2.30.2