From nobody Fri Dec 19 04:06:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF7C7C433FE for ; Wed, 23 Nov 2022 09:42:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238129AbiKWJmx (ORCPT ); Wed, 23 Nov 2022 04:42:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238119AbiKWJl7 (ORCPT ); Wed, 23 Nov 2022 04:41:59 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D0E45A6DE for ; Wed, 23 Nov 2022 01:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669196314; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3Ue4Fy+YA0IMAcpbUeiAy+Mm1ILff9j4snIOtf29MKo=; b=e2mCgtlznLubfJqzIemf7alE5155aJ1elvq6K/7fJdl/qDqvr+rpXWO6hVei1rWdwuwbrM uIVTOTkZ8qItgjNo61ZaxZ1WZGX16UETu75h/S+if2QAFL73EhdTNd79bNc/uK+UlQYBQU 3O7o/Xdr5SY0RI4yAD6Ltd4hF2HDvj13JUT0QuLzlHKfeHKlDL+/BfD0xcHJvzQ3VeNLBt zhoJPInbwSV88jyKDAl/gbeguTI052HVmghLyoQUgHx17B+AhfS8UrYlryZBlHLp2y/8EN uIn0BFOsKbrnfkrDkjxL4QV03h/dhUN03xqbOtbwFoBJoOm/m0xN7rXeLNdk1w== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-642-jykHJpJyMPGJrnPrnSVHEw-1; Wed, 23 Nov 2022 04:38:33 -0500 X-MC-Unique: jykHJpJyMPGJrnPrnSVHEw-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Wed, 23 Nov 2022 01:38:26 -0800 From: Rahul Tanwar To: Rahul Tanwar , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , Subject: [PATCH v4 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Date: Wed, 23 Nov 2022 17:38:17 +0800 Message-ID: <20221123093820.21161-2-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123093820.21161-1-rtanwar@maxlinear.com> References: <20221123093820.21161-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel's APIC family of interrupt controllers support local APIC (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic & ioapic from text to YAML schema. Separate lapic & ioapic schemas. Addditionally, add description which was missing in text file and add few more required standard properties which were also missing in text file. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../intel,ce4100-ioapic.txt | 26 -------- .../intel,ce4100-ioapic.yaml | 62 +++++++++++++++++++ .../intel,ce4100-lapic.yaml | 49 +++++++++++++++ 3 files changed, 111 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-lapic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-i= oapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible =3D "intel,ce4100-ioapic"; - #interrupt-cells =3D <2>; - - Device's interrupt property: - - interrupts =3D

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible =3D "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.yaml new file mode 100644 index 000000000000..25d549220c2a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-i= oapic.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioap= ic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) + +maintainers: + - Rahul Tanwar + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for I/O APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-ioapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + ioapic1: interrupt-controller@fec00000 { + compatible =3D "intel,ce4100-ioapic"; + reg =3D <0xfec00000 0x1000>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-lapic.yaml new file mode 100644 index 000000000000..88f320ef4616 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapi= c.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) + +maintainers: + - Rahul Tanwar + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for local APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-lapic + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + lapic0: interrupt-controller@fee00000 { + compatible =3D "intel,ce4100-lapic"; + reg =3D <0xfee00000 0x1000>; + }; --=20 2.17.1 From nobody Fri Dec 19 04:06:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BCC5C4332F for ; Wed, 23 Nov 2022 09:43:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238113AbiKWJnd (ORCPT ); Wed, 23 Nov 2022 04:43:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238063AbiKWJmQ (ORCPT ); Wed, 23 Nov 2022 04:42:16 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.129.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB1AB8C09D for ; Wed, 23 Nov 2022 01:38:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669196327; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xYvIQAHPDOiWXe8EWBzkMn7p0TefXGQ9AkwC3ZjhxhU=; b=WnYVCqLM61jRItci/3t2j6xUZuWIVg1mXO31SPsPiVV1YZRxFg8Ee5dBUN/wls55MSp2OU 0+wDz4348Q7oJk7HBGbLWi48CZwXjVPcEAbnpv7WtUZei6zYAP5guiQnR15epTiao5izdQ FcQ0Q8lAZMgd06W+anyVJi6mmH2NwmrAe/FwvnNJZjiBgnFlO3Iy2h1sI+eJu57fvEyjdp 05k1vIDr2AQUAc79PvTT5gwz8yIQ2gGc+WyT1Eu4jPZLlyQhR0xBkeC2s471R8L4dLtCoE E6Ugq21Udu+JubbMOMRg+wSZ5RYYOeX+6vfuWOT+rHAkFdAIpaBkdFwSfLNO2w== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-515-AsJdrIqOMfK1371Dc64gSg-2; Wed, 23 Nov 2022 04:38:38 -0500 X-MC-Unique: AsJdrIqOMfK1371Dc64gSg-2 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Wed, 23 Nov 2022 01:38:30 -0800 From: Rahul Tanwar To: Rahul Tanwar , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , Subject: [PATCH v4 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Date: Wed, 23 Nov 2022 17:38:18 +0800 Message-ID: <20221123093820.21161-3-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123093820.21161-1-rtanwar@maxlinear.com> References: <20221123093820.21161-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-lapic.yaml index 88f320ef4616..ef47cb657335 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml @@ -35,6 +35,19 @@ properties: reg: maxItems: 1 =20 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mod= e. + For ACPI or MPS spec compliant systems, it is figured out by some re= ad + only bit field/s available in their respective defined data structur= es. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt del= ivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -46,4 +59,5 @@ examples: lapic0: interrupt-controller@fee00000 { compatible =3D "intel,ce4100-lapic"; reg =3D <0xfee00000 0x1000>; + intel,virtual-wire-mode; }; --=20 2.17.1 From nobody Fri Dec 19 04:06:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD0E1C4332F for ; Wed, 23 Nov 2022 09:43:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238189AbiKWJn0 (ORCPT ); Wed, 23 Nov 2022 04:43:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237962AbiKWJmK (ORCPT ); Wed, 23 Nov 2022 04:42:10 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB5C0781A4 for ; Wed, 23 Nov 2022 01:38:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669196324; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AkBrFNa8JXU1rnG3IW0QD6QbjBzAOYoAULmyjQGwhog=; b=JdyvyQft1X1DOmja3c9CY9xrxBwIWLWSMhdbwfwEQ6Qm6htucgG48SSmQXHTLAP44k3gnn hHvAitD50U9BM7yAywReZSd4YVR0iggzvsjU4hg/JBaw0PCcmbWpc1+64OtxqRmLU2OfXf pf3Cp2JATQHz0HaTFzbiG51BLWj6kn+vG3VSv1JyguUpQgMcHIaxWRaHTNjzfp4tTDhqxN KttAZYhpXBubj1Od0tmTyJvmVlOwRPfMYNg75fOjlItnbMviildbop8LhH1P2bXCpCKPNH cjfKWFeZPLqFhOJNP0ZDBxQzqsOFEHrCvwsNijyespTCWlqIHarlbBydbV7Uhg== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-88-nuRbVBA0PV69qlDqrUJNnw-1; Wed, 23 Nov 2022 04:38:42 -0500 X-MC-Unique: nuRbVBA0PV69qlDqrUJNnw-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Wed, 23 Nov 2022 01:38:34 -0800 From: Rahul Tanwar To: Rahul Tanwar , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , Subject: [PATCH v4 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Date: Wed, 23 Nov 2022 17:38:19 +0800 Message-ID: <20221123093820.21161-4-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123093820.21161-1-rtanwar@maxlinear.com> References: <20221123093820.21161-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use latest available pr_lvl() instead of older printk(KERN_LVL) Just a upgrade of print utilities usage no functional changes. Reviewed-by: Andy Shevchenko Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5cd51f25f446..fcc6f1b7818f 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -248,7 +248,7 @@ static void __init dtb_add_ioapic(struct device_node *d= n) =20 ret =3D of_address_to_resource(dn, 0, &r); if (ret) { - printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); + pr_err("Can't obtain address from device node %pOF.\n", dn); return; } mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); @@ -265,7 +265,7 @@ static void __init dtb_ioapic_setup(void) of_ioapic =3D 1; return; } - printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); + pr_err("Error: No information about IO-APIC in OF.\n"); } #else static void __init dtb_ioapic_setup(void) {} --=20 2.17.1 From nobody Fri Dec 19 04:06:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2FA0C433FE for ; Wed, 23 Nov 2022 09:43:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238193AbiKWJng (ORCPT ); Wed, 23 Nov 2022 04:43:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238069AbiKWJmR (ORCPT ); Wed, 23 Nov 2022 04:42:17 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.129.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A3F382BC2 for ; Wed, 23 Nov 2022 01:38:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669196328; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Mc2NS0olCt0qUzsLi0zWfYaDeL0jAmHwQjCqJZ5SsT8=; b=An+fYJ1ak9yv+HUO0ga2BpCsZPO9Df4pTvxFghvP0cW+824ALgkMGhicTZYJmSsrjo8JUb n/AalJCBwe7cUsK6gN6bpL9fE6QQNEJVeCulSGGy7/y0Q+uS30bz3vHHvUUnwReV6I9CpG gnDyCXKPOxnxoPZ+yHwg/eg8WuOY7iKvSz5fOymXM7/jG7+rksyPkuuJpCAmO2BlKTVtw0 IhcAhG2H7JDhflKokTTm2H4jg1KkPSV6bsjA4HT3yGKQF3+PmhmfNh5fqIVtkUfHe8/fGE ciJ+2v/1G3CDfGY3CWfqUXQpn7HbEO4buyJiNWYEMS2RpMTpJWTVujB4ji+30A== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-665-BZZ1RMddN-WSVjCg2PoA3Q-1; Wed, 23 Nov 2022 04:38:47 -0500 X-MC-Unique: BZZ1RMddN-WSVjCg2PoA3Q-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Wed, 23 Nov 2022 01:38:39 -0800 From: Rahul Tanwar To: Rahul Tanwar , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , Subject: [PATCH v4 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Date: Wed, 23 Nov 2022 17:38:20 +0800 Message-ID: <20221123093820.21161-5-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123093820.21161-1-rtanwar@maxlinear.com> References: <20221123093820.21161-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Presently, init/boot time interrupt delivery mode is enumerated only for ACPI enabled systems by parsing MADT table or for older systems by parsing MP table. But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This causes boot time crash for platforms which do not use 8259 compliant legacy PIC. Add support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index fcc6f1b7818f..458e43490414 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) return; } smp_found_config =3D 1; - pic_mode =3D 1; + if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { + pr_info("Virtual Wire compatibility mode.\n"); + pic_mode =3D 0; + } else { + pr_info("IMCR and PIC compatibility mode.\n"); + pic_mode =3D 1; + } + register_lapic_address(lapic_addr); } =20 --=20 2.17.1