From nobody Thu Apr 16 00:54:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBEA2C4321E for ; Wed, 23 Nov 2022 09:15:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237280AbiKWJPO (ORCPT ); Wed, 23 Nov 2022 04:15:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237271AbiKWJPI (ORCPT ); Wed, 23 Nov 2022 04:15:08 -0500 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F92A87578; Wed, 23 Nov 2022 01:15:06 -0800 (PST) Received: from dggpeml500023.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4NHFnP2GyFzmV6V; Wed, 23 Nov 2022 17:14:33 +0800 (CST) Received: from ubuntu1804.huawei.com (10.67.174.58) by dggpeml500023.china.huawei.com (7.185.36.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Wed, 23 Nov 2022 17:15:04 +0800 From: Xiu Jianfeng To: , , , CC: , , , Subject: [PATCH v2] clk: rockchip: Fix memory leak in rockchip_clk_register_pll() Date: Wed, 23 Nov 2022 17:12:01 +0800 Message-ID: <20221123091201.199819-1-xiujianfeng@huawei.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.67.174.58] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500023.china.huawei.com (7.185.36.114) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If clk_register() fails, @pll->rate_table may have allocated memory by kmemdup(), so it needs to be freed, otherwise will cause memory leak issue, this patch fixes it. Fixes: 90c590254051 ("clk: rockchip: add clock type for pll clocks and pll = used on rk3066") Signed-off-by: Xiu Jianfeng --- v2: move kfree(pll->rate_table) to the err_pll block --- drivers/clk/rockchip/clk-pll.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 4b9840994295..2d42eb628926 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1197,6 +1197,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip= _clk_provider *ctx, return mux_clk; =20 err_pll: + kfree(pll->rate_table); clk_unregister(mux_clk); mux_clk =3D pll_clk; err_mux: --=20 2.17.1