From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36325C433FE for ; Wed, 23 Nov 2022 07:48:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229479AbiKWHs5 (ORCPT ); Wed, 23 Nov 2022 02:48:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235616AbiKWHsp (ORCPT ); Wed, 23 Nov 2022 02:48:45 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28052ECCE9 for ; Tue, 22 Nov 2022 23:48:42 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id q96-20020a17090a1b6900b00218b8f9035cso1113806pjq.5 for ; Tue, 22 Nov 2022 23:48:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qEZJoTwhQ3gMKVRNOyr1QQaSSeZV4Cc6rt58FdaM0ug=; b=T1b7VEEleMjpIKF5hl4CzQavZ639wHFKorulZTx9Bb+TUJk7XU1LPMm0Gmn87Gfthm Rg38SkGksnP/4/docKQY/s+m+Rykbi4GkvR/yUEGQbhcAE79KpcYUDTJs/WYpwFK/foo ApG3F5JLqDiloW216TJHQa/z71tQpld0df179spbUCTuZ8uwsexIYQeXguhU/+qQKJ+8 Dsl/AY7xbLFJ3kUUY9nRMHdyUs9+O8DNi0VNHm9NKNDSgZzHyOozOuyZlEAvrmikYXJd xxUoxdL/E5nbuoR1H1kuYbKW3E5YYiQURmoTtieCAGuYxV3JZRh3iHBclzc6N6tfJZy1 v73g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qEZJoTwhQ3gMKVRNOyr1QQaSSeZV4Cc6rt58FdaM0ug=; b=xWYmDCDOcAdNFGh/Py34ym781peiEe0jF5HYfHyJUlEnQNSKpy92m+ClE7zaIuQjoS X5XXiJSRpAmiqz40sYcPwUrjpuWd3446gehSF0ivCI2L2IsdsiIsL1SE7FbOlfEtcxFm 82CJGedUnvqnHxnXoKvrIYmBWdJjI226/s09dVUuBfN1lKvim52XY084tY0F2Zjp4xa6 qB5GxfqTQ5C6xUq/6EHVSbQmVh8Hy4fDC27P6YvhZ0J4r9elNbyinx8l0GEZl5MQqi8+ pdR3b3y8Z+bA0OU2BBz8jahKNcZcz3SLn9ICA9HSL1fh5d8Hn+0hPIOu71d2xJ1JPdB9 tudw== X-Gm-Message-State: ANoB5pmR9FUleEBTPc4mzZ1VfLOjzgCV9yGmkXMF7f4HcbZtzCs1UVkN E1sZoBjpNsl503u4nU0/rR/K X-Google-Smtp-Source: AA0mqf4kVuMW5FcbHtjO5FqfYjL4hacm1PmBX8Z+CPL2JkDNu3/OYU/CRZGh96Zc/rlqnqoE9a115Q== X-Received: by 2002:a17:90a:ca13:b0:218:cf25:1e7a with SMTP id x19-20020a17090aca1300b00218cf251e7amr6783916pjt.29.1669189721600; Tue, 22 Nov 2022 23:48:41 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.48.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:48:40 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 01/20] phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions Date: Wed, 23 Nov 2022 13:18:07 +0530 Message-Id: <20221123074826.95369-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Following the other QMP PHY drivers like PCIe, let's remove the "_tbl" suffix from the qmp_phy_init_tbl definitions. This helps in maintaining the uniformity across all of the QMP PHY drivers. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 130 ++++++++++++------------ 1 file changed, 65 insertions(+), 65 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index c08d34ad1313..047f06c3313a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -107,7 +107,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPH= Y_LAYOUT_SIZE] =3D { [QPHY_SW_RESET] =3D QPHY_V4_PCS_UFS_SW_RESET, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -156,12 +156,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -175,7 +175,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl= [] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -231,12 +231,12 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), @@ -254,7 +254,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f), @@ -266,7 +266,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), @@ -308,13 +308,13 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -333,7 +333,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -344,7 +344,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -374,7 +374,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -383,7 +383,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -421,7 +421,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_t= bl[] =3D { =20 }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -431,7 +431,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -461,7 +461,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -473,7 +473,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -513,7 +513,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -660,12 +660,12 @@ static const char * const qmp_phy_vreg_l[] =3D { static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes_tbl), - .tx_tbl =3D msm8996_ufs_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx_tbl), - .rx_tbl =3D msm8996_ufs_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx_tbl), + .serdes_tbl =3D msm8996_ufs_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes), + .tx_tbl =3D msm8996_ufs_tx, + .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx), + .rx_tbl =3D msm8996_ufs_rx, + .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx), =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -685,14 +685,14 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), - .tx_tbl =3D sdm845_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx_tbl), - .rx_tbl =3D sdm845_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx_tbl), - .pcs_tbl =3D sdm845_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), + .serdes_tbl =3D sdm845_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx_tbl =3D sdm845_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx_tbl =3D sdm845_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs_tbl =3D sdm845_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -709,14 +709,14 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), - .tx_tbl =3D sm6115_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx_tbl), - .rx_tbl =3D sm6115_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx_tbl), - .pcs_tbl =3D sm6115_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), + .serdes_tbl =3D sm6115_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx_tbl =3D sm6115_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx_tbl =3D sm6115_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs_tbl =3D sm6115_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -732,14 +732,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), - .tx_tbl =3D sm8150_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx_tbl), - .rx_tbl =3D sm8150_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx_tbl), - .pcs_tbl =3D sm8150_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8150_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx_tbl =3D sm8150_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx_tbl =3D sm8150_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs_tbl =3D sm8150_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -754,14 +754,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -776,14 +776,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FC8BC4321E for ; Wed, 23 Nov 2022 07:49:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236090AbiKWHtA (ORCPT ); Wed, 23 Nov 2022 02:49:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236051AbiKWHst (ORCPT ); Wed, 23 Nov 2022 02:48:49 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B013ECCE9 for ; Tue, 22 Nov 2022 23:48:48 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id p12so15930349plq.4 for ; Tue, 22 Nov 2022 23:48:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Su1NIZYU8/terDobSHxKGADJDrW1hfmKOqGKgPRAUt8=; b=pJQMn8glJWI/WtsSCZuR38phcR3RnPDZadpfmuWniRa+NG+YvaOMtJ3Rjz3Au6AcBi B8YclqGtNRSuQ8m8xU3tIwwhWGbDWSqlFbVsOFamvEA5VzhCrbeW9i1MJe1PRuDfqsjT kC4gtRUSSkafguTsnMlZJvdh4fsR74fdDHh2IPs/p7hTG/Ssx9KPZ97qmG8gnDMo+ryl UqjUn4XX0bNNAOm7Dg/cRUXV7woD6xSOawfsaXsDTQ0Ak8u0udpAlRSxFhJmeuViw/Ku i8zRL2RuCSHZ1Whqb92iUAngplF4sZyMZbf+4rRMuOP48lQRhBmksse2bKXrj235QKiS rOCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Su1NIZYU8/terDobSHxKGADJDrW1hfmKOqGKgPRAUt8=; b=YmLwKdYE8NghPFvxTwKULx4WL7BuYj96S5a8oN9DplhYTPGBbX9+XbN64/RA4bEJQA bYCLnL6Z6T4C1/Af6dIIg0mPphlQ7dUBBfgqwS8F6OfvPRHQeBNqehO90fvxOHm8+A/S BJqsd2rznZ8qE+x11jgv+rc9m0EMXnZsy9MiSSO3ZxqnR4eYcHIHMeUvJHG+6nDcF6Xv kI0vkldmJWyDRUuV1ozlndLNmzKcyBQ7QMJnObw/YvuK3FZkhLjY++lWjqtkGByFrKMu XsQFOexrqJtJHsxWVuWT8AAZL9YaYCp7ro/3owfwxMntnxcyjvvU96dZlcLmjynqExy1 QBjA== X-Gm-Message-State: ANoB5pm/tCkfGnEAD865RNAaAq2wI+7xsWEvaoF3rdokQPehGCT6By8O 3kd06kblJ5UQFiPj2v7saHIV X-Google-Smtp-Source: AA0mqf47FBzHG1woI8Q6XhWCuFsPxS/TLIZpVMhQ+otr4WA2+UfS+eZAX8zuJr+FOHgH86k1kGoXvw== X-Received: by 2002:a17:902:f707:b0:176:b0ce:3472 with SMTP id h7-20020a170902f70700b00176b0ce3472mr20126577plo.169.1669189727526; Tue, 22 Nov 2022 23:48:47 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.48.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:48:46 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 02/20] phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions Date: Wed, 23 Nov 2022 13:18:08 +0530 Message-Id: <20221123074826.95369-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 047f06c3313a..443f2714a8f1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -107,7 +107,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPH= Y_LAYOUT_SIZE] =3D { [QPHY_SW_RESET] =3D QPHY_V4_PCS_UFS_SW_RESET, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -156,12 +156,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -657,15 +657,15 @@ static const char * const qmp_phy_vreg_l[] =3D { "vdda-phy", "vdda-pll", }; =20 -static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { +static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes), - .tx_tbl =3D msm8996_ufs_tx, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx), - .rx_tbl =3D msm8996_ufs_rx, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx), + .serdes_tbl =3D msm8996_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx_tbl =3D msm8996_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), + .rx_tbl =3D msm8996_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -1146,7 +1146,7 @@ static int qmp_ufs_create(struct device *dev, struct = device_node *np, int id, static const struct of_device_id qmp_ufs_of_match_table[] =3D { { .compatible =3D "qcom,msm8996-qmp-ufs-phy", - .data =3D &msm8996_ufs_cfg, + .data =3D &msm8996_ufsphy_cfg, }, { .compatible =3D "qcom,msm8998-qmp-ufs-phy", .data =3D &sdm845_ufsphy_cfg, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A15D7C3A59F for ; Wed, 23 Nov 2022 07:49:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236133AbiKWHtE (ORCPT ); Wed, 23 Nov 2022 02:49:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236054AbiKWHsz (ORCPT ); Wed, 23 Nov 2022 02:48:55 -0500 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BDAFFA717 for ; Tue, 22 Nov 2022 23:48:54 -0800 (PST) Received: by mail-pg1-x52f.google.com with SMTP id 62so16061459pgb.13 for ; Tue, 22 Nov 2022 23:48:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ikUhsMB1K+IImCkguofeQ85gazjJuE8IZCvzMOqkVlc=; b=N6BWzgRM3GU2/ZA+dngSkO6sddxPS8QvVv9bGitcc/SXgncaMWgeCWJNRTPBh9w0Fp HoELivWACbVF6BP8dLXxT8Cq4N5u//RgqiIK+iDDXqhASkd4P2A+DWcUIIL53EkqKMO+ yL/tT6pYGM2SiugPqnnE9k++/AT6+gXji7fHMAzv9gxe94fAopacgp8kwNsE6a5VpNTD LsKA29379+w5qrrgDNv22B6ccCpUwDVrrR3Eg3xlIW1kwCvW/kfTZAsO08FPtuB0ARtX na4jAKntKm1PDnVZ06+cxi/B1/Z5hSfmWEqTVVWbHur9zwoWIhQt3FHiWpxOKNi2TeVK hhKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ikUhsMB1K+IImCkguofeQ85gazjJuE8IZCvzMOqkVlc=; b=RDgzQOwC7Gf+xLbDLhJSvqGVJmz8JmNfQzxQtN8AlnB5uVSgA2+D2rZXSHnGgzNkGO 1XHsRlIIeBpWikS0eNyvM9rD+LahDa/rLPp8asXopCuhDaglY2tS+IFoqX1w3AccMJrD 7kqFjDLIYzYPxceQMmvgX3ZasmE5/mNPlDa6ovuNl5R76ph8qm1pq3G1s9kon9x+Fict dBLb/uc6Xkj/b4G2ipIfzhCyOUt18tjoT7qx7KIK21SGMJN16OlACbbslKY1j90rkIzn iq4J5CoV+SHcABHUKqTbeEBxqSSc9HOYj21NLvMfFDc8VExZDBDUfUvL0UtrXIQYMvMw uYcg== X-Gm-Message-State: ANoB5pmFiKVhp8R4GBnTpncV9KMVW5BN1KfveOCBIO3UGFXdHPkYIot4 vw9lA8AexQ0UOw8n0VSGBaoP X-Google-Smtp-Source: AA0mqf7F0L+mYTQ2+e6gAYvmxg1wwhlAoeAH8qLK20IrK9dx+Rymck5OAcM9bwT77aVUN2iN7mbS8w== X-Received: by 2002:a63:f003:0:b0:45f:bf86:c917 with SMTP id k3-20020a63f003000000b0045fbf86c917mr25393662pgh.201.1669189733521; Tue, 22 Nov 2022 23:48:53 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.48.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:48:52 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 03/20] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct Date: Wed, 23 Nov 2022 13:18:09 +0530 Message-Id: <20221123074826.95369-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 192 ++++++++++++++---------- 1 file changed, 112 insertions(+), 80 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 443f2714a8f1..3b7b36e32f5d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -531,19 +531,24 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pc= s[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +struct qmp_phy_cfg_tbls { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes; + int serdes_num; + const struct qmp_phy_init_tbl *tx; + int tx_num; + const struct qmp_phy_init_tbl *rx; + int rx_num; + const struct qmp_phy_init_tbl *pcs; + int pcs_num; +}; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { int lanes; =20 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_cfg_tbls tbls; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -660,12 +665,14 @@ static const char * const qmp_phy_vreg_l[] =3D { static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), - .tx_tbl =3D msm8996_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), - .rx_tbl =3D msm8996_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), + .tbls =3D { + .serdes =3D msm8996_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx =3D msm8996_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), + .rx =3D msm8996_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), + }, =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -685,14 +692,16 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), - .tx_tbl =3D sdm845_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), - .rx_tbl =3D sdm845_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), - .pcs_tbl =3D sdm845_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + .tbls =3D { + .serdes =3D sdm845_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx =3D sdm845_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx =3D sdm845_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs =3D sdm845_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -709,14 +718,16 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), - .tx_tbl =3D sm6115_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), - .rx_tbl =3D sm6115_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), - .pcs_tbl =3D sm6115_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm6115_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx =3D sm6115_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx =3D sm6115_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs =3D sm6115_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -732,14 +743,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), - .tx_tbl =3D sm8150_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), - .rx_tbl =3D sm8150_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), - .pcs_tbl =3D sm8150_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -754,14 +767,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -776,14 +791,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -826,16 +843,50 @@ static void qmp_ufs_configure(void __iomem *base, qmp_ufs_configure_lane(base, regs, tbl, num, 0xff); } =20 -static int qmp_ufs_serdes_init(struct qmp_phy *qphy) +static void qmp_ufs_serdes_init(struct qmp_phy *qphy, const struct qmp_phy= _cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg =3D qphy->cfg; void __iomem *serdes =3D qphy->serdes; - const struct qmp_phy_init_tbl *serdes_tbl =3D cfg->serdes_tbl; - int serdes_tbl_num =3D cfg->serdes_tbl_num; =20 - qmp_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + if (!tbls) + return; + + qmp_ufs_configure(serdes, cfg->regs, tbls->serdes, tbls->serdes_num); +} =20 - return 0; +static void qmp_ufs_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_= cfg_tbls *tbls) +{ + const struct qmp_phy_cfg *cfg =3D qphy->cfg; + void __iomem *tx =3D qphy->tx; + void __iomem *rx =3D qphy->rx; + + qmp_ufs_configure_lane(tx, cfg->regs, tbls->tx, tbls->tx_num, 1); + + if (cfg->lanes >=3D 2) + qmp_ufs_configure_lane(qphy->tx2, cfg->regs, tbls->tx, tbls->tx_num, 2); + + qmp_ufs_configure_lane(rx, cfg->regs, tbls->rx, tbls->rx_num, 1); + + if (cfg->lanes >=3D 2) + qmp_ufs_configure_lane(qphy->rx2, cfg->regs, tbls->rx, tbls->rx_num, 2); +} + +static void qmp_ufs_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cf= g_tbls *tbls) +{ + const struct qmp_phy_cfg *cfg =3D qphy->cfg; + void __iomem *pcs =3D qphy->pcs; + + if (!tbls) + return; + + qmp_ufs_configure(pcs, cfg->regs, tbls->pcs, tbls->pcs_num); +} + +static void qmp_ufs_init_registers(struct qmp_phy *qphy, const struct qmp_= phy_cfg *cfg) +{ + qmp_ufs_serdes_init(qphy, &cfg->tbls); + qmp_ufs_lanes_init(qphy, &cfg->tbls); + qmp_ufs_pcs_init(qphy, &cfg->tbls); } =20 static int qmp_ufs_com_init(struct qmp_phy *qphy) @@ -933,31 +984,12 @@ static int qmp_ufs_power_on(struct phy *phy) struct qmp_phy *qphy =3D phy_get_drvdata(phy); struct qcom_qmp *qmp =3D qphy->qmp; const struct qmp_phy_cfg *cfg =3D qphy->cfg; - void __iomem *tx =3D qphy->tx; - void __iomem *rx =3D qphy->rx; void __iomem *pcs =3D qphy->pcs; void __iomem *status; unsigned int mask, val, ready; int ret; =20 - qmp_ufs_serdes_init(qphy); - - /* Tx, Rx, and PCS configurations */ - qmp_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - - if (cfg->lanes >=3D 2) { - qmp_ufs_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); - } - - qmp_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - - if (cfg->lanes >=3D 2) { - qmp_ufs_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); - } - - qmp_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_ufs_init_registers(qphy, cfg); =20 ret =3D reset_control_deassert(qmp->ufs_reset); if (ret) --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE84CC4321E for ; Wed, 23 Nov 2022 07:49:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236164AbiKWHte (ORCPT ); Wed, 23 Nov 2022 02:49:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236054AbiKWHtJ (ORCPT ); Wed, 23 Nov 2022 02:49:09 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3E65FA731 for ; Tue, 22 Nov 2022 23:49:00 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id r18so16078239pgr.12 for ; Tue, 22 Nov 2022 23:49:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=17DUm1BHWO+9+pCruDSwXwFA2DWaV0LvIvFJmkLFp/8=; b=szHgLObizdRjU8Uhq446KGApvra49ApA5BIcru3Ey/6Do2T56DSsWvR5g9jLZHc476 MSlgWT8MIf8p+f/sxml/uIYI/OfERwdOxx5UrTrYqsRwWRZFHtuRDyZJ5Rx4UxQu9KFi bHD+ee5c55d9SFNG5Pwp6XrqCpbVMI7Noo/UYKv4oy6hdO4XzjAQT10xIo8VNGpS1lk0 Z20HdS4+82s4XqLdrE2uV7dVCOiPbh7w+y4ldF3k1iYZtAtLx40Dsl+kKesa4AdfKKoU pHw3S/F4iNp6nK3l1atD4eXQ9Qt72dI6wxGZlj7nTc6si+4kweYwgd/xG8XerHXUsBmF dhZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=17DUm1BHWO+9+pCruDSwXwFA2DWaV0LvIvFJmkLFp/8=; b=4J7Hjgsv7V/Nap/mhJRAagi1NDvQTUG2dWeQ75ychb4I0hHY04OtS9gOglIQQB8ova U3OFZQB3MJfXuOTOXPSNJYxLuc8qXKjjsf6ZZUzzNAZGSIBQwqYv0OMt1AO+pUIOatMa CAfIbg0zXnMiLSI6h4qpxYuyHfsaaq/WTOZQ2wTmP2ZWTmBwmL3tBbM2hUmMURN+9FLQ A1MOrx4EkfNp42ZnYSTs7XbxnOTukqo2YSju5xT3C8pawBjoUnqLPN7e7VUucP/MIFE2 jPskaR/hBE4LkxIhVdeTT3873h+2Ipf132D1wM8VpIRoizvoNkiQE6IW2P0Kaj5DBnkv ZbIw== X-Gm-Message-State: ANoB5plQb7n2tBTWBzpgSIN0ya4C5jdSaph2lHvwooAXDbBInKuePMqp VG+u4EKXCc8WU62o2iT7FyuZ X-Google-Smtp-Source: AA0mqf5p/xJXOPvTRxbeUxcJCUOhwd51+9yIUCWj0RA8EwvAT98+ugBHbeaX8uInPuYuqUPJ+lVyfQ== X-Received: by 2002:a63:5007:0:b0:45f:beda:4116 with SMTP id e7-20020a635007000000b0045fbeda4116mr8165671pgb.618.1669189739616; Tue, 22 Nov 2022 23:48:59 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:48:58 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 04/20] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Date: Wed, 23 Nov 2022 13:18:10 +0530 Message-Id: <20221123074826.95369-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 3b7b36e32f5d..694b1d6c1f9c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -20,6 +20,8 @@ #include #include =20 +#include + #include =20 #include "phy-qcom-qmp.h" @@ -549,6 +551,8 @@ struct qmp_phy_cfg { =20 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_cfg_tbls tbls; + /* Additional sequence for HS Series B */ + const struct qmp_phy_cfg_tbls tbls_hs_b; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -582,6 +586,7 @@ struct qmp_phy_cfg { * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc * @qmp: QMP phy to which this lane belongs + * @mode: PHY mode configured by the UFS driver */ struct qmp_phy { struct phy *phy; @@ -594,6 +599,7 @@ struct qmp_phy { void __iomem *rx2; void __iomem *pcs_misc; struct qcom_qmp *qmp; + u32 mode; }; =20 /** @@ -885,6 +891,8 @@ static void qmp_ufs_pcs_init(struct qmp_phy *qphy, cons= t struct qmp_phy_cfg_tbls static void qmp_ufs_init_registers(struct qmp_phy *qphy, const struct qmp_= phy_cfg *cfg) { qmp_ufs_serdes_init(qphy, &cfg->tbls); + if (qphy->mode =3D=3D PHY_MODE_UFS_HS_B) + qmp_ufs_serdes_init(qphy, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qphy, &cfg->tbls); qmp_ufs_pcs_init(qphy, &cfg->tbls); } @@ -1073,6 +1081,15 @@ static int qmp_ufs_disable(struct phy *phy) return qmp_ufs_exit(phy); } =20 +static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submo= de) +{ + struct qmp_phy *qphy =3D phy_get_drvdata(phy); + + qphy->mode =3D mode; + + return 0; +} + static int qmp_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg = *cfg) { struct qcom_qmp *qmp =3D dev_get_drvdata(dev); @@ -1108,6 +1125,7 @@ static int qmp_ufs_clk_init(struct device *dev, const= struct qmp_phy_cfg *cfg) static const struct phy_ops qcom_qmp_ufs_ops =3D { .power_on =3D qmp_ufs_enable, .power_off =3D qmp_ufs_disable, + .set_mode =3D qmp_ufs_set_mode, .owner =3D THIS_MODULE, }; =20 --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DA79C433FE for ; Wed, 23 Nov 2022 07:49:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236094AbiKWHt3 (ORCPT ); Wed, 23 Nov 2022 02:49:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236305AbiKWHtO (ORCPT ); Wed, 23 Nov 2022 02:49:14 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F1DCFAEBB for ; Tue, 22 Nov 2022 23:49:06 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso1243524pjt.0 for ; Tue, 22 Nov 2022 23:49:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lZ+MoCrzv+gfQQlMeW5WbAnmXRNL0HTRmdnVMxPl0cY=; b=rTVDZnzCbprEOjWhm+OWYfVd3SVRZhCSkGhAb8ZFiWFAeIq8pMUGmVrS1DV0RCTXz4 RtvpSBrlsnnWjpUMod2BPbot9BTJ+fSHYSU5Gj2CTBsIss4fTozJfFcMU32rYErsCJeI JxANAljaFOM8fe4KPlHmCPaJ2G+XP7IDfOyp/TXWEgO9OtobP8RmOBRHznIaDFYQ2zCO bZ1XXLB2c0XDOh3o1H8w0qGReU5YYqlQvLVUXgEPPH01qpcWxITAhYt6iwijrg7ALIHl s9vnUys5X2DW6GwJwbkveHNxwbPwKUQhV6OSKF5V098puOuEVHiAcO6tqUA5PcowdSNO BQxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lZ+MoCrzv+gfQQlMeW5WbAnmXRNL0HTRmdnVMxPl0cY=; b=7MRLh0XqEchBHTKiUOkc1UDHKU7pd5TIUgNiVf4O2QWu0DxgOlhpCzf8ScHeVI1vA9 Zt5qqBB2La+2VHW1tt6qPC3fcyOKfGqJZ6kRZv3XH7b1AfhLQnQ2K7leoU21d450vueJ Z+DPQUplTaPnM0S9W8m0iEWniFXXBMoVh8uVIODmicrphkysBYdOoR4ofLhaYzAr8lHM C/QeRjdFP34hbZTXgl7HBexFr03v4Fm1eG4YskRq2HzV7ntXrXlDCJr3Jukepc0NSBQa Y/o+vUt3P02qsPfTMaFHMeEcg8EWFsW2d/mQX/8X/Mx6CnCqd1M0cjCuAS2hcmwQoUlY /DLQ== X-Gm-Message-State: ANoB5pm/ZLeyQfdVR75p4knMLLDqvD0I/yxOOOVGNy72eVpflGzTMoQb vgVvoFr0vOlQGT023BWeC+fc X-Google-Smtp-Source: AA0mqf7t739TpdcQ3ko/yzBAkk8CJjjbrbWW5NFxLKP3l+rmMq+NCR2N2qvUCyO4zu8PHoRl++US/g== X-Received: by 2002:a17:90a:5918:b0:213:df25:7e8a with SMTP id k24-20020a17090a591800b00213df257e8amr36106769pji.154.1669189745683; Tue, 22 Nov 2022 23:49:05 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:04 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 05/20] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Date: Wed, 23 Nov 2022 13:18:11 +0530 Message-Id: <20221123074826.95369-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 694b1d6c1f9c..1b6e76bf82e5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -553,6 +553,8 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls; /* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tbls tbls_hs_b; + /* Additional sequence for HS G4 */ + const struct qmp_phy_cfg_tbls tbls_hs_g4; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -587,6 +589,7 @@ struct qmp_phy_cfg { * @pcs_misc: iomapped memory space for lane's pcs_misc * @qmp: QMP phy to which this lane belongs * @mode: PHY mode configured by the UFS driver + * @submode: PHY submode configured by the UFS driver */ struct qmp_phy { struct phy *phy; @@ -600,6 +603,7 @@ struct qmp_phy { void __iomem *pcs_misc; struct qcom_qmp *qmp; u32 mode; + u32 submode; }; =20 /** @@ -894,7 +898,11 @@ static void qmp_ufs_init_registers(struct qmp_phy *qph= y, const struct qmp_phy_cf if (qphy->mode =3D=3D PHY_MODE_UFS_HS_B) qmp_ufs_serdes_init(qphy, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qphy, &cfg->tbls); + if (qphy->submode =3D=3D UFS_HS_G4) + qmp_ufs_lanes_init(qphy, &cfg->tbls_hs_g4); qmp_ufs_pcs_init(qphy, &cfg->tbls); + if (qphy->submode =3D=3D UFS_HS_G4) + qmp_ufs_pcs_init(qphy, &cfg->tbls_hs_g4); } =20 static int qmp_ufs_com_init(struct qmp_phy *qphy) @@ -1086,6 +1094,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy= _mode mode, int submode) struct qmp_phy *qphy =3D phy_get_drvdata(phy); =20 qphy->mode =3D mode; + qphy->submode =3D submode; =20 return 0; } --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2626C4708B for ; Wed, 23 Nov 2022 07:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236195AbiKWHuG (ORCPT ); Wed, 23 Nov 2022 02:50:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236338AbiKWHtV (ORCPT ); Wed, 23 Nov 2022 02:49:21 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A026FA72A for ; Tue, 22 Nov 2022 23:49:12 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id l22-20020a17090a3f1600b00212fbbcfb78so1199122pjc.3 for ; Tue, 22 Nov 2022 23:49:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c56xjSGwfmMkQ772Tv3sbW08SSFT7wB9ddz0u8vdom0=; b=li29VgAjITZO6SGICTr8jhTQdZaqyt3QloHToZFrlSGFlR52juA/aWYv5sW73RWZ8a cAdXa34eBmfA6Z+P0dn2seGG0LQouJYhQIXDBGhUOatQU0m8/Dzhbpet9+3aEsQ7R7jA lgTgp4nepX26Wwj9nfQcVSCZKWc2H4Cemu2XXEMVhQt3o/NHJNB8S36lU8NG5b9CkYmj 2aRXl5legESQs5vpgUmyFL3rp8x/BvWNdI65+nN0FOKu4v3npUhNFbvqAD1nqyr4gxks bBodox4aEHDxBZuwSi2BzlaAtoOLg3iryZVh0bAeTd9Z7xPvTyvYJ3lWiZYo0P7zjnGp 5S8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c56xjSGwfmMkQ772Tv3sbW08SSFT7wB9ddz0u8vdom0=; b=SjupTwiKgM6XhXthfnCdftA62kHD0zYt6MX1g1Ewtoa2BGseC6fKLxLNOnPF5qBsCW LfntFNxmQil0+1MuPNVzVieL0MAq2jGmZhPhi51e0NWWZPJ5A78qSweNKVkR38tVFAVh HCVj3t3LaE3TPV1XYFyqZoC/GZv6gAo2oGYveTYnalNICc9t7u/0GNItTu9fAWR8j7ao uHp+Z0K8DWQa6cWrwS4wlZ1PzJiwnYH4uWTuBenSGIbsOXpJwYvpqme4OzLkJU2sKDO/ TAYnDaAbH9OvWkVsXSlOCdD7V9miDflrPsuEAXRzfurz84SPYRTeYJm5IitqsNp+aory JYvg== X-Gm-Message-State: ANoB5pkk3KlgA2nonjgbU8qLIkpc/wcot8V7hdLTajFmsuZex+padwdV CqS1eHnolUstZK7FUF0N4N6L X-Google-Smtp-Source: AA0mqf7NTKwctMv+R4DVCUMIJsdTpjLzt1ZHzlUtNiQ1vtiHoKHPf9Spa1heVuWusQhxhHryUQ35fQ== X-Received: by 2002:a17:902:cf4b:b0:186:7a1d:b6ee with SMTP id e11-20020a170902cf4b00b001867a1db6eemr12532417plg.67.1669189751898; Tue, 22 Nov 2022 23:49:11 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:11 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 06/20] phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b Date: Wed, 23 Nov 2022 13:18:12 +0530 Message-Id: <20221123074826.95369-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 33 +++++++++++++++++++++---- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 1b6e76bf82e5..f6a962df9df1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -228,8 +228,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -305,8 +306,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -371,8 +373,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -420,7 +423,6 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[]= =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), - }; =20 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { @@ -458,8 +460,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -712,6 +715,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .pcs =3D sdm845_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sdm845_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -738,6 +745,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .pcs =3D sm6115_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm6115_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -763,6 +774,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .pcs =3D sm8150_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -787,6 +802,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -811,6 +830,10 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD069C47088 for ; Wed, 23 Nov 2022 07:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236184AbiKWHuA (ORCPT ); Wed, 23 Nov 2022 02:50:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235916AbiKWHtX (ORCPT ); Wed, 23 Nov 2022 02:49:23 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AC86FA735 for ; Tue, 22 Nov 2022 23:49:18 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id j10-20020a17090aeb0a00b00218dfce36e5so1214576pjz.1 for ; Tue, 22 Nov 2022 23:49:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sTz6Ll8Gs0xoeDCO8dLxC3S4/zJEIzg+DDVekYPXgJQ=; b=lI1w6Dh7ejOQk94fGrk7q7JhaZvkFQ0FJvBwUj14wInvjq2B1Q8oOLz0AprW6EosL1 l1gZMmc2z4Bre77GR/pSuHtt2iELJMhaqDMJ8CPGpGPELO9bWA/nhsy8kNPEJiIMnNJq hoTkw2v+3cf8jYcMjq9P32FXtaB1pHyv3iJ4HLxwBE5fe8h5WRM0KUPBBa2kkyOm5pGx CQmK7hxDZNGJVK1dpqP+idwEGfViUbX0imL/6fhtdjXL+ZK9czdTLuNWJuuRpZ6oUmI5 22ws0FvQqUjJm5fl1YtoUgGmEOfwWkWCq7zwDj7NsH0a6V4a1oiRFt66seDX2V9Cc3EU QZBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sTz6Ll8Gs0xoeDCO8dLxC3S4/zJEIzg+DDVekYPXgJQ=; b=zpAaoHI77ItrVjQeeNKZi7tTxc2VKYy6RTRNgaA2zq8mTLiInD5IkRJGzqyMRSr9YT YH69dQs0vqA9CGeQdeB4tFMNw3T0wUMXPgt2JBcXfQfkfKzKGBYPhyojvn7eU4D78EWF RD+/kz9VUSqy8oE7Wvku42u/0OO9SjSR4d/LTJuupI1JWgJ+5GTflZNSC7eDMATuRciN ypVvGork2X+iwHlxbyR1tftMyGdIqfeAibw9+wiOCQWxRUupxoGXfzzN2rGLpY8vNXtb dT1zgvISShPO41BRf9UoZqQ2sEehqExnsfIR0W+wIuEMDQLmUr3d9lzujA2w5LS3iAUu 5ddQ== X-Gm-Message-State: ANoB5pkLwQYhe8xs6gPENs6yIleldGK0LDMSRHfRa7V+JRP8usKsviJO Nt4RAgAJGlXpAWihsn/G9ORQ X-Google-Smtp-Source: AA0mqf7lgRKWCiPjmygSZJxRVBlM43RcPUGb0SERrh7Uy6E3umAnpwWt0zg+O6eZ1pvBoTXnkGFJGw== X-Received: by 2002:a17:903:2c2:b0:182:631a:ef28 with SMTP id s2-20020a17090302c200b00182631aef28mr7249584plk.46.1669189758029; Tue, 22 Nov 2022 23:49:18 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:17 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 07/20] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC Date: Wed, 23 Nov 2022 13:18:13 +0530 Message-Id: <20221123074826.95369-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index f6a962df9df1..98ebaf898a50 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -388,6 +388,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), @@ -425,6 +429,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), @@ -435,6 +458,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -778,6 +806,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .serdes =3D sm8150_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8150_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), + .rx =3D sm8150_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), + .pcs =3D sm8150_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B78F2C47089 for ; Wed, 23 Nov 2022 07:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236109AbiKWHt5 (ORCPT ); Wed, 23 Nov 2022 02:49:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236110AbiKWHtZ (ORCPT ); Wed, 23 Nov 2022 02:49:25 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FDD7FAEA8 for ; Tue, 22 Nov 2022 23:49:24 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id io19so15924979plb.8 for ; Tue, 22 Nov 2022 23:49:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hg08mVmbyiFP9E6Z2PHg4XW3jll6IEe2Kyqu7cYnyxo=; b=rhA03McCzm2tbgQAfVlulnKmZMzII8Jz/JuV3yBJceN2ArgPZ2jrg8TtBza3skhG+H Xo7xWCeRUL+Sr29C75isrQ+lIqP7VQTtWFv2j9TE/JZH1MAfwHL/NImAqIqfTq00SxT+ K/t1D+a+V8IxhCtJ2mOo1QgmpykiPLorndzBBCx2q/SD4zIrU+uHWFKIB7ziyZUDRlCf LFDHo5wifIjPa/EiGtu4mxEaJQeFMi5PsGMh730A+i+VEp1rhfQI8F9TZyUw4+hQY+fg WyeKzs1xWRhNFXg5xpxytf0mslhbaZXlAhClbcGiYq+8yOcYBfY8I4aoQLtEgcAmfpji bIfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hg08mVmbyiFP9E6Z2PHg4XW3jll6IEe2Kyqu7cYnyxo=; b=Yu+biWqeO1mtuA9PuW29DcfTv9lyxXvED4HCXtQiBPmnuPg/pXvZimxTDZEXgQUazb mraKrGqQR8NQBG3Nz/c+wy+2Zg2h4ZQnUaXRynp2SiUkSM8pnpM+f/9TuTd4XBiC4AEp iFMRRHBpzFxG1IpQzSXuC/zCSpB2e+lJHMekh7factg6B+tlyPzPSLsUBbeZDznqvgWN VBtSvqHx09jzjUDEt7Dlh7wfmGthsBoGqDB8AwtCdK5zGcm1+WLPjXMtQbwamwrSrV5W I+l3bJ+mVa3uuvvCtF7rVMAjIuZtLbdKpWtF8HnFzZY+GNezZL/XjMcITdi1tGH/QN3Y lLrg== X-Gm-Message-State: ANoB5pn34ktzVpjXkoPEUffD9xNf0gmTwWQgIOI7kDFzABsYwIyUB5v2 i93soH6GcxZC4rXNUXBwEk3b X-Google-Smtp-Source: AA0mqf7lImoiViK9D8sXUI+GsipScgWGH4Rd0Lt9u2sHEw3i7ecS7aqYvtbaH1Sq2IrtYuSMKzeQsw== X-Received: by 2002:a17:90a:be11:b0:218:c83e:4735 with SMTP id a17-20020a17090abe1100b00218c83e4735mr9212963pjs.9.1669189763826; Tue, 22 Nov 2022 23:49:23 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:22 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 08/20] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Date: Wed, 23 Nov 2022 13:18:14 +0530 Message-Id: <20221123074826.95369-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 66 ++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 98ebaf898a50..d39ee28fb6a3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -463,6 +463,34 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_= g4_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), }; =20 +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -825,6 +853,42 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .phy_status =3D PHYSTATUS, }; =20 +static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D { + .lanes =3D 2, + + .tbls =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tbls_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 =3D { + .tx =3D sm8250_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx =3D sm8250_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), + .pcs =3D sm8150_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list =3D sdm845_ufs_phy_clk_l, + .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8150_ufsphy_regs_layout, + + .start_ctrl =3D SERDES_START, + .pwrdn_ctrl =3D SW_PWRDN, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 @@ -1288,7 +1352,7 @@ static const struct of_device_id qmp_ufs_of_match_tab= le[] =3D { .data =3D &sm8150_ufsphy_cfg, }, { .compatible =3D "qcom,sm8250-qmp-ufs-phy", - .data =3D &sm8150_ufsphy_cfg, + .data =3D &sm8250_ufsphy_cfg, }, { .compatible =3D "qcom,sm8350-qmp-ufs-phy", .data =3D &sm8350_ufsphy_cfg, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2B5CC47089 for ; Wed, 23 Nov 2022 07:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236242AbiKWHua (ORCPT ); Wed, 23 Nov 2022 02:50:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236216AbiKWHtn (ORCPT ); Wed, 23 Nov 2022 02:49:43 -0500 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4B52FBA95 for ; Tue, 22 Nov 2022 23:49:29 -0800 (PST) Received: by mail-pf1-x42c.google.com with SMTP id b4so495154pfb.9 for ; Tue, 22 Nov 2022 23:49:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=80dm928QYjr4oaUe835NN0o7sI/usasikkVJKdylirU=; b=WRVpYhROFvYz65xUbt//WOCcZo2HgsBSoiXl2Q3Ne20Ne4BN3GFVoxtgxgbccnZvLS pv04Zmdx/RMc0DlJUDEkIHKgtwlChJYrcZWHGfNQMtKeya9eYHwdoFvEhGgQ67rNk41e YqAg6gXjnJET2hbT0QUcqm33o3UivXWLzkA7Pq9r4MKYGo84ZPNRqXpyPS7hUXZgS6KK Dic7KWjLZlS/GUNtbQj1LGWlDTvLoofpwP5bwUOl+F8gW3bDWwuciu8LaFdvmEsqj9Jw FoOLUD1tH6mxuq3LwpLK5dgQ8WjWUOKRrW5lg1tkHsicMznq7Arw8UonE2hAn4jx6mPv c0xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=80dm928QYjr4oaUe835NN0o7sI/usasikkVJKdylirU=; b=H+hdfKvhTA2hLBKWQUFCQR5DbvMZiq1N2VHSOw+jCHA+iKEpmCu9b/CflAR+N9hFIH 9HwTbk8phKoeHRWNwJ6xXcfS+zue3ZMVobCiFckBM7gvbzqGVkJhJLBTAc7iIEYFwUFA TuymJNFjRxNclNwkA7WJI+hO8n82JMeYty/cZ2RFYX9YTIs2Pb0g3CAUdQh+nUjrQwtZ Ko36lmj1HtO0/1OLytII6EvoTM5dE+yL4/b3Hgg1mGa4hlhQ+n0I7tQaYW9b9pmTwyxv SPTdiE+JxL89JgW2dWnFdObqgjNrbJ6mRvYRPtN2cToUXe5qOfUZWBNR3w9n/rUjzbFP ZAWw== X-Gm-Message-State: ANoB5pn/hwPfWw97O+SmWC4wy8AJeHEaJkR5x6HGMcWpyUTywlMb8qL/ jq0RQ5qwsS7aDMkEtX2lM+uV X-Google-Smtp-Source: AA0mqf6Snp7j5kDvcsF+9bMBzw+agm/tT1gkk+PUrpXpKcXUq0qzTWx9Xu2gZT0tp8E79AK9NkFcPw== X-Received: by 2002:a63:461d:0:b0:456:d859:2143 with SMTP id t29-20020a63461d000000b00456d8592143mr6261885pga.396.1669189769348; Tue, 22 Nov 2022 23:49:29 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:28 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 09/20] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC Date: Wed, 23 Nov 2022 13:18:15 +0530 Message-Id: <20221123074826.95369-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8450 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Signed-off-by: Manivannan Sadhasivam --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 48 +++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/q= ualcomm/phy-qcom-qmp-pcs-ufs-v5.h index bcca23493b7e..3aa4232f84a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -13,6 +13,7 @@ #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index d39ee28fb6a3..7a77db3196db 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -592,6 +592,46 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), + /* + * Following registers are not required for HS-G4 mode, but since these + * are already programmed as part of previous init sequence, we'll program + * again with reset values. + */ + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x2d), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xb0), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xff), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x15), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), +}; + struct qmp_phy_cfg_tbls { /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes; @@ -934,6 +974,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D16E5C4708B for ; Wed, 23 Nov 2022 07:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235631AbiKWHue (ORCPT ); Wed, 23 Nov 2022 02:50:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236351AbiKWHtu (ORCPT ); Wed, 23 Nov 2022 02:49:50 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA6DEFC703 for ; Tue, 22 Nov 2022 23:49:35 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id a1-20020a17090abe0100b00218a7df7789so1189836pjs.5 for ; Tue, 22 Nov 2022 23:49:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SEImNrrGJCLJR7lpSd2nSHN0zzQY9fzqQ71zihD+hPY=; b=tNBVG03lVciDsO8t9kXfWt8DMe+QTB1RLzHEeAA+gi5fa25FWcL3vvPPKbbt9GO3Sf XQrOQdaEvEE205S9ivqL47uUIc8rbtQv2at1gVO3XEhPrihcfjfc3BcWu6qYmAddB+D2 Pp8ajE/jhpo/VjAIMq1FfRaS3SQbaBzPdLLDcO8kuOaYrp6NMfltFZ9uU8rG0K0UfPoa +BpkcxjQ4/dxOnbGO4ikiVdpGJMv80iV1DHg4UHgtnux8JfHnbSF2rqTRefAuCHQVCPW WVmY/k1h6UVxcXYsU67U3vQXpqTlK3v08iT/mz3DuYxOgSczaz0WG0a24/ohf1LjwuNt kRfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SEImNrrGJCLJR7lpSd2nSHN0zzQY9fzqQ71zihD+hPY=; b=JIm9rJttsWdkqTeaMXuohTgMtlnHOn2RUbPGULp19GAjeqnwAQDM6hMFioJ18p2PFl EhQvrYq3BRgpFFg5CDAUKZAe2Hxqv6Dz9VymiwgMpFb+5+d8YQ90xRna77WJtmCgs8SI 53/gEEfjNxjuSeAe77njnaCZUrOYbm80bQfdg4+1osem47JhkzbiLWJvBQOsztrmGFao cpHpfh7l8IbmESmbGSGCfzqfVLZpBFwBwIxiUqMJiKxrZX85CVOk/iihLwzTPesm6A+v YJ7jHN7xKMrvJ6njTz6XyJETUT5jZ2RxWSd4uiOSJ/Bvf0V4Hbgh8+VAI7CJayEyeaJ0 94PA== X-Gm-Message-State: ANoB5plW+u+IbP2tfQdrQ7oTrB771hSS8hN+TDftk2a8TnjoqbNY6pcR r8ewyOfAgNYbsNRE9Wu0W9FK X-Google-Smtp-Source: AA0mqf7DJGG7ecY7teJvrrYsGj2x1etItgZsLZjyKRwrt+lLBpO+r/ijGXe0c8nugcqZqSiTjRBKSw== X-Received: by 2002:a17:902:f1c5:b0:189:39e4:c0ed with SMTP id e5-20020a170902f1c500b0018939e4c0edmr4505578plc.108.1669189775133; Tue, 22 Nov 2022 23:49:35 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:34 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 10/20] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Date: Wed, 23 Nov 2022 13:18:16 +0530 Message-Id: <20221123074826.95369-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" goto in error path is useful if the function needs to do cleanup other than returning the error code. But in this driver, goto statements are used for just returning the error code in many places. This really makes it hard to read the code. So let's get rid of those goto statements and just return the error code directly. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 100 +++++++++++++++--------------------- 1 file changed, 41 insertions(+), 59 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8ad1415e10b6..7cd996ac180b 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -110,7 +110,7 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_= host *host) =20 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) { - int err =3D 0; + int err; struct device *dev =3D host->hba->dev; =20 if (host->is_lane_clks_enabled) @@ -119,7 +119,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) err =3D ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", host->rx_l0_sync_clk); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", host->tx_l0_sync_clk); @@ -137,7 +137,8 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) goto disable_rx_l1; =20 host->is_lane_clks_enabled =3D true; - goto out; + + return 0; =20 disable_rx_l1: clk_disable_unprepare(host->rx_l1_sync_clk); @@ -145,7 +146,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) clk_disable_unprepare(host->tx_l0_sync_clk); disable_rx_l0: clk_disable_unprepare(host->rx_l0_sync_clk); -out: + return err; } =20 @@ -160,25 +161,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_ho= st *host) err =3D ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", &host->rx_l0_sync_clk, false); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", &host->tx_l0_sync_clk, false); if (err) - goto out; + return err; =20 /* In case of single lane per direction, don't read lane1 clocks */ if (host->hba->lanes_per_direction > 1) { err =3D ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", &host->rx_l1_sync_clk, false); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", &host->tx_l1_sync_clk, true); } -out: - return err; + + return 0; } =20 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) @@ -241,7 +242,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) =20 if (!host->core_reset) { dev_warn(hba->dev, "%s: reset control not set\n", __func__); - goto out; + return 0; } =20 reenable_intr =3D hba->is_irq_enabled; @@ -252,7 +253,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) if (ret) { dev_err(hba->dev, "%s: core_reset assert failed, err =3D %d\n", __func__, ret); - goto out; + return ret; } =20 /* @@ -274,15 +275,14 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) hba->is_irq_enabled =3D true; } =20 -out: - return ret; + return 0; } =20 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct phy *phy =3D host->generic_phy; - int ret =3D 0; + int ret; bool is_rate_B =3D UFS_QCOM_LIMIT_HS_RATE =3D=3D PA_HS_MODE_B; =20 /* Reset UFS Host Controller and PHY */ @@ -299,7 +299,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) if (ret) { dev_err(hba->dev, "%s: phy init failed, ret =3D %d\n", __func__, ret); - goto out; + return ret; } =20 /* power on phy - start serdes and phy's power and clocks */ @@ -316,7 +316,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) =20 out_disable_phy: phy_exit(phy); -out: + return ret; } =20 @@ -374,7 +374,6 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *h= ba, static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate, bool update_link_startup_timer) { - int ret =3D 0; struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct ufs_clk_info *clki; u32 core_clk_period_in_ns; @@ -409,11 +408,11 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, * Aggregation logic. */ if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) - goto out; + return 0; =20 if (gear =3D=3D 0) { dev_err(hba->dev, "%s: invalid gear =3D %d\n", __func__, gear); - goto out_error; + return -EINVAL; } =20 list_for_each_entry(clki, &hba->clk_list_head, list) { @@ -436,7 +435,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32= gear, } =20 if (ufs_qcom_cap_qunipro(host)) - goto out; + return 0; =20 core_clk_period_in_ns =3D NSEC_PER_SEC / core_clk_rate; core_clk_period_in_ns <<=3D OFFSET_CLK_NS_REG; @@ -451,7 +450,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32= gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rA)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D hs_fr_table_rA[gear-1][1]; } else if (rate =3D=3D PA_HS_MODE_B) { @@ -460,13 +459,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rB)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D hs_fr_table_rB[gear-1][1]; } else { dev_err(hba->dev, "%s: invalid rate =3D %d\n", __func__, rate); - goto out_error; + return -EINVAL; } break; case SLOWAUTO_MODE: @@ -476,14 +475,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(pwm_fr_table)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D pwm_fr_table[gear-1][1]; break; case UNCHANGED: default: dev_err(hba->dev, "%s: invalid mode =3D %d\n", __func__, hs); - goto out_error; + return -EINVAL; } =20 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=3D @@ -507,12 +506,8 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u3= 2 gear, */ mb(); } - goto out; =20 -out_error: - ret =3D -EINVAL; -out: - return ret; + return 0; } =20 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, @@ -527,8 +522,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba = *hba, 0, true)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); - err =3D -EINVAL; - goto out; + return -EINVAL; } =20 if (ufs_qcom_cap_qunipro(host)) @@ -554,7 +548,6 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba = *hba, break; } =20 -out: return err; } =20 @@ -691,8 +684,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, =20 if (!dev_req_params) { pr_err("%s: incoming dev_req_params is NULL\n", __func__); - ret =3D -EINVAL; - goto out; + return -EINVAL; } =20 switch (status) { @@ -720,7 +712,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, if (ret) { pr_err("%s: failed to determine capabilities\n", __func__); - goto out; + return ret; } =20 /* enable the device ref clock before changing to HS mode */ @@ -761,7 +753,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, ret =3D -EINVAL; break; } -out: + return ret; } =20 @@ -773,14 +765,11 @@ static int ufs_qcom_quirk_host_pa_saveconfigtime(stru= ct ufs_hba *hba) err =3D ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), &pa_vs_config_reg1); if (err) - goto out; + return err; =20 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ - err =3D ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), (pa_vs_config_reg1 | (1 << 12))); - -out: - return err; } =20 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) @@ -957,9 +946,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) =20 host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); if (!host) { - err =3D -ENOMEM; dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); - goto out; + return -ENOMEM; } =20 /* Make a two way bind between the qcom host and the hba */ @@ -980,10 +968,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->rcdev.owner =3D dev->driver->owner; host->rcdev.nr_resets =3D 1; err =3D devm_reset_controller_register(dev, &host->rcdev); - if (err) { + if (err) dev_warn(dev, "Failed to register reset controller\n"); - err =3D 0; - } =20 if (!has_acpi_companion(dev)) { host->generic_phy =3D devm_phy_get(dev, "ufsphy"); @@ -1049,17 +1035,16 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->dbg_print_en |=3D UFS_QCOM_DEFAULT_DBG_PRINT_EN; ufs_qcom_get_default_testbus_cfg(host); err =3D ufs_qcom_testbus_config(host); - if (err) { + if (err) + /* Failure is non-fatal */ dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); - err =3D 0; - } =20 - goto out; + return 0; =20 out_variant_clear: ufshcd_set_variant(hba, NULL); -out: + return err; } =20 @@ -1085,7 +1070,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_di= v(struct ufs_hba *hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), &core_clk_ctrl_reg); if (err) - goto out; + return err; =20 core_clk_ctrl_reg &=3D ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; core_clk_ctrl_reg |=3D clk_cycles; @@ -1093,11 +1078,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_d= iv(struct ufs_hba *hba, /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &=3D ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; =20 - err =3D ufshcd_dme_set(hba, + return ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), core_clk_ctrl_reg); -out: - return err; } =20 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) @@ -1180,7 +1163,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, =20 if (err || !dev_req_params) { ufshcd_uic_hibern8_exit(hba); - goto out; + return err; } =20 ufs_qcom_cfg_timers(hba, @@ -1191,8 +1174,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, ufshcd_uic_hibern8_exit(hba); } =20 -out: - return err; + return 0; } =20 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E10C9C4708A for ; Wed, 23 Nov 2022 07:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236303AbiKWHui (ORCPT ); Wed, 23 Nov 2022 02:50:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236358AbiKWHtw (ORCPT ); Wed, 23 Nov 2022 02:49:52 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8DB7FBAB7 for ; Tue, 22 Nov 2022 23:49:41 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id b11so15255899pjp.2 for ; Tue, 22 Nov 2022 23:49:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RgfrCdEhXykVwBp3nVTN7WEjo711kZc0QKngTjXB/aU=; b=AtlYAIpauMotfnGl9jZIW/bs4OXPXsjqMu/t5z9waPiXFr+ZLGRbncdtrZ+xccgL4+ ZmWoyRIerO0JwGuCWf/VI+7gQqE+MUj6zBip/uqsxxDyg1qsczhyP3aMIAMszq6wr1uT bvFGr/B3cXBhK3TwmA+4nva6/xx/GXYIuAotU4KTZD+L1N7ZnEmkpTwSY5Jn06EOxKzb P4q0Zq5/Poxrkm9YwDjFn6nmkNumTkGb4plFjP2kDx/4Yfk2B7wD59uFzzwxettvuGnU SYP7ZrQWuuFm/kC+Wpxd02pJmDrp07ZWFVYLe5Qo3gZUy2xUNnZcqj4WWJFO6OSX5TJZ M8eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RgfrCdEhXykVwBp3nVTN7WEjo711kZc0QKngTjXB/aU=; b=P8PfQGCUd8ZoXgz6U7hrTbT5OOdCJdDvoc3VR0PK55pnGWeSZKeSqGOGz2CLfdgcKL mRSmXPW/RA4MilmR6VlbZNcUpPBrS0ob64fHA7QazKl5HhkZn/Wh27uJ0quxqIqmdSvK OBUD1Bw9er6d4wGKBq1gBK/tb1bH3VYhQcUBV/qrCriwvWcH9q5uOqiq3eJZTlXTd0B7 Mwv7ZU010XZ94ac/Sx5bM8hHCsuSwDK94Y1ZCnIT35ShUrvrO/K72Yx1RzzAnI64qsSs cjxUGNAk7DPuE8ElhKNtMo6zEz7wzT6U6b7IT6sjGnueZvh2cwbulx3Soype9ZD7IHgE jJvw== X-Gm-Message-State: ANoB5pm2TFpscrfFi/CqGDYf0OGeVNpcb9LNyUD53XovAfSVcYfL6fga ltpk+HUFo5BVz7FJtSasbsmz X-Google-Smtp-Source: AA0mqf7MKZeCvXf5M5XLWkX+Fqjhqr3Su01CfEQgrc8qo0XLX61I+9/B/AjkA+tkBnMTRD/m+311Tg== X-Received: by 2002:a17:90a:e2c2:b0:218:825e:17f8 with SMTP id fr2-20020a17090ae2c200b00218825e17f8mr25546559pjb.129.1669189780946; Tue, 22 Nov 2022 23:49:40 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:40 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 11/20] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Date: Wed, 23 Nov 2022 13:18:17 +0530 Message-Id: <20221123074826.95369-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the reset assert and deassert callbacks, the supplied "id" is not used at all and only the hba reset is performed all the time. So there is no reason to use a WARN_ON on the "id". Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 7cd996ac180b..8bb0f4415f1a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -895,8 +895,6 @@ ufs_qcom_reset_assert(struct reset_controller_dev *rcde= v, unsigned long id) { struct ufs_qcom_host *host =3D rcdev_to_ufs_host(rcdev); =20 - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_assert_reset(host->hba); /* provide 1ms delay to let the reset pulse propagate. */ usleep_range(1000, 1100); @@ -908,8 +906,6 @@ ufs_qcom_reset_deassert(struct reset_controller_dev *rc= dev, unsigned long id) { struct ufs_qcom_host *host =3D rcdev_to_ufs_host(rcdev); =20 - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_deassert_reset(host->hba); =20 /* --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F1DAC43217 for ; Wed, 23 Nov 2022 07:51:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236178AbiKWHvE (ORCPT ); Wed, 23 Nov 2022 02:51:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236373AbiKWHty (ORCPT ); Wed, 23 Nov 2022 02:49:54 -0500 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 982A59A26C for ; Tue, 22 Nov 2022 23:49:47 -0800 (PST) Received: by mail-pf1-x435.google.com with SMTP id 140so16619842pfz.6 for ; Tue, 22 Nov 2022 23:49:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=wUq6WL4djnJwsxvN1wYxuCnno9lsf6UoLa5/ahB19bSFnw/2RTLYZZlREaB2lhRbir lrR6BM2sfcWwDXLt/h6cO+jwX93SVOj4G6mKFLU1WmIZHtkxpP4wWu3r5iO4z/2tkG3P qJhHMGdo0zyJ4EEC936GDf9IXale45dNjGY4ST5eVp+SW3huBItJ4bPF1lSucYK0xESW Hc68DTKv0EXDtzQ1EEZYI257Sy4+iDXOuoL4/wpjSNksJQRo1wgzNViwFV/PUhbPWE0E aMON3M8s+S+Z58BZMW62O7Bjnqw/JAKLpUj+fZfWZ2TnF+2GSiDsg1ZUyXjsYbu6p0hS 6ICQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=jaeec3mCwoQ9LEduaryALko48lkdo6sM8voJU5ISnw6EN7IortVuieaawEZk2/xA5S aaPCJ6OrPjOGERXChXvexWlGyzMosXDO9lDH/bibNRk4I2GD+MQG3iZrTerH1ZklFzUB e0cOJZ9p01OzXomTfvK2mVxFfx0J2iq9HqSd4RdTSkno4NNEp75bJSFetOIZWpFstHqy PUM7y6K9DAC3o9rh6UisDsbsjjQZmku+U+CL3fxcvnjDs0kqAH2cLDET0XUPipxr9n9X KqaMfsdSHMlVK+3JiW3cbDDBtjBv9kR3k2U5rRv1Z1ZxmWXp3Fx3KlTTuv4FYJ6fM5I1 3JgQ== X-Gm-Message-State: ANoB5pnuL+jLcaIcyd1+5oerX4sbQ1vgLoiIt2T0QrLQQqNLcBsSZl4V KI7eYQFgRguM1xaW+OcztRQr X-Google-Smtp-Source: AA0mqf6Mtq3CwE43GnB33Scv6zg2lNpAOH3e5wdqEMbp0mtC8rEfnc4NEBIbX7O1KkBJzVg/GwYD1g== X-Received: by 2002:a63:ea52:0:b0:46f:9c0c:8673 with SMTP id l18-20020a63ea52000000b0046f9c0c8673mr8465805pgk.154.1669189786822; Tue, 22 Nov 2022 23:49:46 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:45 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 12/20] scsi: ufs: ufs-qcom: Use bitfields where appropriate Date: Wed, 23 Nov 2022 13:18:18 +0530 Message-Id: <20221123074826.95369-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use bitfield macros where appropriate to simplify the driver. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 44466a395bb5..9d96ac71b27f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -17,12 +17,9 @@ #define DEFAULT_CLK_RATE_HZ 1000000 #define BUS_VECTOR_NAME_LEN 32 =20 -#define UFS_HW_VER_MAJOR_SHFT (28) -#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) -#define UFS_HW_VER_MINOR_SHFT (16) -#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) -#define UFS_HW_VER_STEP_SHFT (0) -#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) +#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) +#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) +#define UFS_HW_VER_STEP_MASK GENMASK(15, 0) =20 /* vendor specific pre-defined parameters */ #define SLOW 1 @@ -76,24 +73,28 @@ enum { #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) =20 /* bit definitions for REG_UFS_CFG1 register */ -#define QUNIPRO_SEL 0x1 -#define UTP_DBG_RAMS_EN 0x20000 +#define QUNIPRO_SEL BIT(0) +#define UFS_PHY_SOFT_RESET BIT(1) +#define UTP_DBG_RAMS_EN BIT(17) #define TEST_BUS_EN BIT(18) #define TEST_BUS_SEL GENMASK(22, 19) #define UFS_REG_TEST_BUS_EN BIT(30) =20 +#define UFS_PHY_RESET_ENABLE 1 +#define UFS_PHY_RESET_DISABLE 0 + /* bit definitions for REG_UFS_CFG2 register */ -#define UAWM_HW_CGC_EN (1 << 0) -#define UARM_HW_CGC_EN (1 << 1) -#define TXUC_HW_CGC_EN (1 << 2) -#define RXUC_HW_CGC_EN (1 << 3) -#define DFC_HW_CGC_EN (1 << 4) -#define TRLUT_HW_CGC_EN (1 << 5) -#define TMRLUT_HW_CGC_EN (1 << 6) -#define OCSC_HW_CGC_EN (1 << 7) +#define UAWM_HW_CGC_EN BIT(0) +#define UARM_HW_CGC_EN BIT(1) +#define TXUC_HW_CGC_EN BIT(2) +#define RXUC_HW_CGC_EN BIT(3) +#define DFC_HW_CGC_EN BIT(4) +#define TRLUT_HW_CGC_EN BIT(5) +#define TMRLUT_HW_CGC_EN BIT(6) +#define OCSC_HW_CGC_EN BIT(7) =20 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ -#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide = */ +#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 b= its wide */ =20 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ @@ -101,17 +102,11 @@ enum { TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) =20 /* bit offset */ -enum { - OFFSET_UFS_PHY_SOFT_RESET =3D 1, - OFFSET_CLK_NS_REG =3D 10, -}; +#define OFFSET_CLK_NS_REG 0xa =20 /* bit masks */ -enum { - MASK_UFS_PHY_SOFT_RESET =3D 0x2, - MASK_TX_SYMBOL_CLK_1US_REG =3D 0x3FF, - MASK_CLK_NS_REG =3D 0xFFFC00, -}; +#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0) +#define MASK_CLK_NS_REG GENMASK(23, 10) =20 /* QCOM UFS debug print bit mask */ #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0) @@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, { u32 ver =3D ufshcd_readl(hba, REG_UFS_HW_VERSION); =20 - *major =3D (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT; - *minor =3D (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT; - *step =3D (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT; + *major =3D FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); + *minor =3D FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); + *step =3D FIELD_GET(UFS_HW_VER_STEP_MASK, ver); }; =20 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_P= HY_RESET_ENABLE), + REG_UFS_CFG1); =20 /* * Make sure assertion of ufs phy reset is written to @@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba= *hba) =20 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_P= HY_RESET_DISABLE), + REG_UFS_CFG1); =20 /* * Make sure de-assertion of ufs phy reset is written to --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A51A3C47088 for ; Wed, 23 Nov 2022 07:51:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236319AbiKWHvH (ORCPT ); Wed, 23 Nov 2022 02:51:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236313AbiKWHuJ (ORCPT ); Wed, 23 Nov 2022 02:50:09 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71293FA72B for ; Tue, 22 Nov 2022 23:49:53 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id g10so15909394plo.11 for ; Tue, 22 Nov 2022 23:49:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ff060FMlh2MHBX3ga6yMFYN0UyVEYS40VqwmLXF4PCQ=; b=DJBZrYbtm9X/QLJ/W0BggBinY/2j9h/csY7y1RXj4ibeLojZMPOM79qLxjtvmX+0ef qHTZgJHFtB32vZURoOJwLrNnSQaX+2bXlf8zHuE6hiZvRxi7W+LWnTCMbLdSEjKKDFtr rKUTqK0DqmheaA9m8c6D41qw7p4fLNAiNy+PHR04AEaVDVbk5EpB+rRgUXGybW134Dfa o4VjElLklHUuz5FiE57L+c8177u3W7udeCaUt7iGmyf7sLEWBSAQ7XWXEHHDp0xcZmxV BS/SqxE5y3XMtTkm4XOZMcntYbiHkMT+O69Uqzk1+oWlwsjgpd+I94tXWMAjZ+a6pFNg B6nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ff060FMlh2MHBX3ga6yMFYN0UyVEYS40VqwmLXF4PCQ=; b=VjL24WGhiNEJCaNeHTi7Gl9gthK5uboJgm3OuK9SsviRwnwTo9Ch2psH9VeUE51i2Y jhiy1RioNIOLzFddE8X0peSkm8R23P6OrAAsgF/T3Nv4bFT+2vRVv6I4WRo6LaN5VV2f 7K4Tn0ak3Qv2HHrYTQrMECgGFU/kvyR8sA08Qsg7cPYb46+zAXxmxTy5uIr8Wli1f00S OEm0MTca+GptIspOs/l5saQL6lXvHlx4SjNJQo52D6msnnPk3MtSClfwoIgIxjwrbCBe 8GWhI4w9ebcUN17kpytK2/u77R5xVvuB7QMIux29GmPU7AiVujas7s8jauZnFLCsWmW2 gnqg== X-Gm-Message-State: ANoB5pn8Y6oNUesIWzh/BmiJCJJdUXJc26X7rqE/pmiAkAG5S6wMHTLa ZQcWyMLmrIeaIPLYX0smn013 X-Google-Smtp-Source: AA0mqf7JrTjVi6IhOYnAnZ7BbIJkXhoSI7J/05AMbqHKIqgMfOzWmGZ4ebVDRyq5ynhxhMb8SwK5Cg== X-Received: by 2002:a17:90a:73c2:b0:200:a7b4:6511 with SMTP id n2-20020a17090a73c200b00200a7b46511mr28487090pjk.101.1669189792943; Tue, 22 Nov 2022 23:49:52 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:52 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 13/20] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Date: Wed, 23 Nov 2022 13:18:19 +0530 Message-Id: <20221123074826.95369-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make use of dev_err_probe() for printing the probe error. Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8bb0f4415f1a..38e2ed749d75 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1441,9 +1441,9 @@ static int ufs_qcom_probe(struct platform_device *pde= v) /* Perform generic probe */ err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); if (err) - dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); + return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); =20 - return err; + return 0; } =20 /** --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9767DC43217 for ; Wed, 23 Nov 2022 07:51:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236217AbiKWHvf (ORCPT ); Wed, 23 Nov 2022 02:51:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236323AbiKWHuM (ORCPT ); Wed, 23 Nov 2022 02:50:12 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFCB6FA73D for ; Tue, 22 Nov 2022 23:49:58 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id b62so16159665pgc.0 for ; Tue, 22 Nov 2022 23:49:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dxBfeAGPJSh5Y/5FKQg+M0y4cyLZHfyLwZKtosIJVD4=; b=hvohjQO8JYIIopMXFu3hU+uN5hELxDhjhQ7dxyj3c+Q/LQ4Fb4Flb51c62NHkSRJNR FO6JfqvdsTm/Ayc9GUj0DD4tkpVcvaF7XH3MFy3Zl7uWWme3K2G7lAhwT/gFjWgejGgV R/DXDHDhUtzAnReZu8ggSAJzA7yDv0X8sSp8abzoUZAdtJli6tU5aYK/P5L9ZE3T3qw8 LcDcjGEBu4HiVgt+A9RioAgoVRtUULYluxAZxExY8ChKkpS7CccBR7iePfNBjbw/QXpi HfBMHw5SPmv4Hw5i8Di256ieI2eTIxYr2QHYim+S5I1Fmx1kHqBKMv5o2AM9QfAsMeQQ eW9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dxBfeAGPJSh5Y/5FKQg+M0y4cyLZHfyLwZKtosIJVD4=; b=QBk4oK1cfswQb1HShxlSVzMbJZCbrDn2DU1PZSGOICIa7NjhHeIEV8pWyDNBfYGyBK BuAVBDe4hbjzVcjRcLD0hvrKTiL9MT0PWAp7V2tphUuPpY8vmwsAXP+O803xm9FDXTvw oFRZKhVtmwkdG2163DURXZ2CKOdYcmznih50arhzUsEkzoBfWnVSeG8b+bNGovH9DRMR gYKbnQIZxUp3rrhFrFKYC26QqS/aYAJKa5ap6AOAcTJk0f/pH/e4yCgi7u1Oj6P7utjJ LTDqZv5wOi1D5SCcGGD6KgQhwwyngnrXVpQT7eZ6sNe4one4iL8YU99wZrY06Op+e+qN 0S2A== X-Gm-Message-State: ANoB5pkC9kzD7JG8yJbS4xkN03zCblB/Fz1VfGc3zBG77of5dQxh6d5m 3Sy1IYm+UPHxvS06gS8Jjj39 X-Google-Smtp-Source: AA0mqf6cWZTcqMQ6iaMD6TbVO8Lgo74SN6zYkHGzRMd58POs8i2QkQeWC7UZd6p4A6tyAaWB6HRKvg== X-Received: by 2002:a63:4c4d:0:b0:46f:8c3a:8b2b with SMTP id m13-20020a634c4d000000b0046f8c3a8b2bmr7051732pgl.477.1669189798376; Tue, 22 Nov 2022 23:49:58 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:49:57 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 14/20] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Date: Wed, 23 Nov 2022 13:18:20 +0530 Message-Id: <20221123074826.95369-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On newer UFS revisions, the register at offset 0xD0 is called, REG_UFS_PARAM0. Since the existing register, RETRY_TIMER_REG is not used anywhere, it is safe to use the new name. Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 9d96ac71b27f..7fe928b82753 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -33,7 +33,8 @@ enum { REG_UFS_TX_SYMBOL_CLK_NS_US =3D 0xC4, REG_UFS_LOCAL_PORT_ID_REG =3D 0xC8, REG_UFS_PA_ERR_CODE =3D 0xCC, - REG_UFS_RETRY_TIMER_REG =3D 0xD0, + /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ + REG_UFS_PARAM0 =3D 0xD0, REG_UFS_PA_LINK_STARTUP_TIMER =3D 0xD8, REG_UFS_CFG1 =3D 0xDC, REG_UFS_CFG2 =3D 0xE0, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF2D0C4332F for ; Wed, 23 Nov 2022 07:51:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236304AbiKWHvj (ORCPT ); Wed, 23 Nov 2022 02:51:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236211AbiKWHu1 (ORCPT ); Wed, 23 Nov 2022 02:50:27 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08A30FC71B for ; Tue, 22 Nov 2022 23:50:04 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id j12so15923323plj.5 for ; Tue, 22 Nov 2022 23:50:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I2Xd0gDlZp0b1F7R46Bn1beu0377yVMDIxRd9gxYrRE=; b=j4a2IZ4M/RPn02KaaMa7o/DiXf8mhGrp8hO1u8giHS105CGBy7ebnfzwcG4Ysm3Z2K kaxfRevnkU72bEifmC5K/ilMeVXZC9kdXRrTFph5Dd+4P+gg5yT0H8eKeBDNCUnZMhtP 8jmhF5FG90qgX6YdP3X5BzL5dHnPipH0647G5o5q7eTUZ14l9ax7zB8kQD3IOmHSbPAp Xrq4yyYFYxZ4ktvd7X0uVK724lPuIJgYS24OpnuTkgzYzkBp76epnP7TMIby91Wvq1aR dRCLodWM9m1RMxYDJD4rlsjA9RGAVl8nD3+7Vki373kL62fuNXYaEOdHVl2WpUu1DKjc 0HTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I2Xd0gDlZp0b1F7R46Bn1beu0377yVMDIxRd9gxYrRE=; b=qxSIoCUcsbcBy1yFNKv1Yk6HKPZZFLJC6nv7XFbAIy/eXfGLtanxbi8W7KvN5ygZN4 S/pZ7p7sc4m71i83uiO8kTy1Mcrn9oteg3lP57sCIqFrD8LwhQrikkqWjdozUsRrv7m2 xGa/x4ERi0Fm2BLqQjMvl4Uo5WNmSsT/qVyNJS1jqnbhZAXGYDLf7fzmRraRIpkj49BT SIooeZnnwfvsZeESJg9UDKRJZbr+rzvpTlvX7FIg1zUNWCg0ilQedT4eU7Z4yXSfqEx/ hdFMb4RGKYQoUVSq6vXbqkpWthDRsijxAQm2TTL+/UYrL7qVc2jyiLr5AhPUA8SrJ/jQ U5lQ== X-Gm-Message-State: ANoB5pkYd/Qp7jl632dkqSNEWWZAE0kRfuIjmnshlrDOwEurRiVn0REA q5Kjhco+4U7nM6Exa9RYgGFk X-Google-Smtp-Source: AA0mqf4EA/xu0LNp5Eeym9s5QmhuOi/k38g2Q5DDLTpsDvRmwE7yo049HbunO3rvytSj8UQTUayfsw== X-Received: by 2002:a17:902:b184:b0:189:1d01:a4ae with SMTP id s4-20020a170902b18400b001891d01a4aemr8039549plr.93.1669189804266; Tue, 22 Nov 2022 23:50:04 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.49.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:50:03 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 15/20] scsi: ufs: core: Add reinit_notify() callback Date: Wed, 23 Nov 2022 13:18:21 +0530 Message-Id: <20221123074826.95369-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" reinit_notify() callback can be used by the UFS controllers to perform changes required for UFS core reinit. Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/core/ufshcd-priv.h | 6 ++++++ include/ufs/ufshcd.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index f68ca33f6ac7..37260c1af9f0 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -226,6 +226,12 @@ static inline void ufshcd_vops_config_scaling_param(st= ruct ufs_hba *hba, hba->vops->config_scaling_param(hba, p, data); } =20 +static inline void ufshcd_vops_reinit_notify(struct ufs_hba *hba) +{ + if (hba->vops && hba->vops->reinit_notify) + hba->vops->reinit_notify(hba); +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; =20 /** diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 9f28349ebcff..09927a011a84 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -297,6 +297,7 @@ struct ufs_pwr_mode_info { * @config_scaling_param: called to configure clock scaling parameters * @program_key: program or evict an inline encryption key * @event_notify: called to notify important events + * @reinit_notify: called to notify UFS core reinit */ struct ufs_hba_variant_ops { const char *name; @@ -335,6 +336,7 @@ struct ufs_hba_variant_ops { const union ufs_crypto_cfg_entry *cfg, int slot); void (*event_notify)(struct ufs_hba *hba, enum ufs_event_type evt, void *data); + void (*reinit_notify)(struct ufs_hba *); }; =20 /* clock gating state */ --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BD95C3A59F for ; Wed, 23 Nov 2022 07:52:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236122AbiKWHwE (ORCPT ); Wed, 23 Nov 2022 02:52:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236365AbiKWHvW (ORCPT ); Wed, 23 Nov 2022 02:51:22 -0500 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2209FAEBD for ; Tue, 22 Nov 2022 23:50:10 -0800 (PST) Received: by mail-pf1-x434.google.com with SMTP id b29so16595959pfp.13 for ; Tue, 22 Nov 2022 23:50:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Xs9R7SPzAS5pOWZNCxb7jU9uBO2AEwyHCVEvHAOYro=; b=xnIcVBVVhreHcdS7Ugnx76iz55CIxjVzKcXg+MoU+KmJuWrTaUBEXS9+FIx/Y0u73z vdCgbI8cTzTHdjUSxoIi/95NV0Vjlxhc70yIy8lliHjCgDKewiee6q1iEgSma6we3Azo T4VlECf+1VJ+oeFF3As5u8ezCHr5bVmigRRYPAG9yTiU46ck8y+wquPdWWK7ITuCm2bo sKdQ7aRcs1rNHa5QQO5gIyCNf1v6mp4G8rXT5eEu9GudQ4qf3UTv8vi+wWNI8K440gks QlJ1qrrg4bEZYFpqu+Sp8/oFR/Xb+uv91V/siAlNJB5diHdFSyKkPniMWfwj6S3K0bLC SJ5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Xs9R7SPzAS5pOWZNCxb7jU9uBO2AEwyHCVEvHAOYro=; b=p0oooQwnFYa831hclFwyPIOsnOFMEQz66Dj8jaA2TGRDy1qOuuC0ujvBfkfMFES9AM pWERLGpnsUW9TeTzu6Wd5k/5bWf6HqOVmsQYnhzvGecZBC7uK0LpqYyQpxrtqBHKFAC1 G2USHi/Cu57IjFneKlkn2jRQvhQqXyNWnE/TQocrlrj9ulgLVGDNk8ww2sixr16Y1boO AtD9UGZ0SuSqawHHfo4cqoSp8KvmTyV01hnlZu9lPLYxpEAugtvVR5m5U6laoxCkc9Qj tx5EKXjN9iCKvcMGZNyymrQonUXrhJFOJEs3zuMNqW+Rahj6QZkpyPYMDO0DHAoXY0Z5 uYPA== X-Gm-Message-State: ANoB5pnfZPSUt2fYhV0ItCEdYKCHSjZsMF4EP1gPGFF0mS6uSnAWgD1x GviuGZgWE1pPCgErWm380qEe X-Google-Smtp-Source: AA0mqf5Qkci9MclBetYKpk99wpyqRldXc/tZtpb53k/xKGLez3Vf4fNonMqHr0wE24M73D9Dz1d/DQ== X-Received: by 2002:a63:230d:0:b0:476:aad3:9122 with SMTP id j13-20020a63230d000000b00476aad39122mr7060304pgj.402.1669189810294; Tue, 22 Nov 2022 23:50:10 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.50.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:50:09 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 16/20] scsi: ufs: core: Add support for reinitializing the UFS device Date: Wed, 23 Nov 2022 13:18:22 +0530 Message-Id: <20221123074826.95369-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some platforms like Qcom, requires the UFS device to be reinitialized after switching to maximum gear speed. So add support for that in UFS core by introducing a new quirk (UFSHCD_CAP_REINIT_AFTER_MAX_GEAR_SWITCH) and doing the reinitialization, if the quirk is enabled by the controller driver. Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/core/ufshcd.c | 63 +++++++++++++++++++++++++++++---------- include/ufs/ufshcd.h | 6 ++++ 2 files changed, 53 insertions(+), 16 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 7256e6c43ca6..c44ffb63d48f 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8161,27 +8161,18 @@ static int ufshcd_add_lus(struct ufs_hba *hba) return ret; } =20 -/** - * ufshcd_probe_hba - probe hba to detect device and initialize it - * @hba: per-adapter instance - * @init_dev_params: whether or not to call ufshcd_device_params_init(). - * - * Execute link-startup and verify device initialization - */ -static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) +static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) { int ret; - unsigned long flags; - ktime_t start =3D ktime_get(); =20 hba->ufshcd_state =3D UFSHCD_STATE_RESET; =20 ret =3D ufshcd_link_startup(hba); if (ret) - goto out; + return ret; =20 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) - goto out; + return ret; =20 /* Debug counters initialization */ ufshcd_clear_dbg_ufs_stats(hba); @@ -8192,12 +8183,12 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bo= ol init_dev_params) /* Verify device initialization by sending NOP OUT UPIU */ ret =3D ufshcd_verify_dev_init(hba); if (ret) - goto out; + return ret; =20 /* Initiate UFS initialization, and waiting until completion */ ret =3D ufshcd_complete_dev_init(hba); if (ret) - goto out; + return ret; =20 /* * Initialize UFS device parameters used by driver, these @@ -8206,7 +8197,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool= init_dev_params) if (init_dev_params) { ret =3D ufshcd_device_params_init(hba); if (ret) - goto out; + return ret; } =20 ufshcd_tune_unipro_params(hba); @@ -8227,11 +8218,51 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bo= ol init_dev_params) if (ret) { dev_err(hba->dev, "%s: Failed setting power mode, err =3D %d\n", __func__, ret); + return ret; + } + } + + return 0; +} + +/** + * ufshcd_probe_hba - probe hba to detect device and initialize it + * @hba: per-adapter instance + * @init_dev_params: whether or not to call ufshcd_device_params_init(). + * + * Execute link-startup and verify device initialization + */ +static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) +{ + ktime_t start =3D ktime_get(); + unsigned long flags; + int ret; + + ret =3D ufshcd_device_init(hba, init_dev_params); + if (ret) + goto out; + + if (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) { + /* Reset the device and controller before doing reinit */ + ufshcd_device_reset(hba); + ufshcd_hba_stop(hba); + ufshcd_vops_reinit_notify(hba); + ret =3D ufshcd_hba_enable(hba); + if (ret) { + dev_err(hba->dev, "Host controller enable failed\n"); + ufshcd_print_evt_hist(hba); + ufshcd_print_host_state(hba); goto out; } - ufshcd_print_pwr_info(hba); + + /* Reinit the device */ + ret =3D ufshcd_device_init(hba, init_dev_params); + if (ret) + goto out; } =20 + ufshcd_print_pwr_info(hba); + /* * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) * and for removable UFS card as well, hence always set the parameter. diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 09927a011a84..d3e8aa7a4207 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -595,6 +595,12 @@ enum ufshcd_quirks { * auto-hibernate capability but it's FASTAUTO only. */ UFSHCD_QUIRK_HIBERN_FASTAUTO =3D 1 << 18, + + /* + * This quirk needs to be enabled if the host controller needs + * to reinit the device after switching to maximum gear. + */ + UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH =3D 1 << 19, }; =20 enum ufshcd_caps { --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47283C433FE for ; Wed, 23 Nov 2022 07:52:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236401AbiKWHwK (ORCPT ); Wed, 23 Nov 2022 02:52:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236373AbiKWHvX (ORCPT ); Wed, 23 Nov 2022 02:51:23 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B6AAFAE90 for ; Tue, 22 Nov 2022 23:50:16 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id io19so15926490plb.8 for ; Tue, 22 Nov 2022 23:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jQW21UMpMMT39kQGkUZ44Bi2KAiI76Uffz4R9s7ZIY4=; b=Q4uifVNUG8xLZiw0nKZzqWhlsFQVjN7R7zmwgdRS/fTSn0Pz18mv37YJD39o+JlZ+U YX50U9RmFIiBE5gaK+qWmu8dehcTfKoU1BOe+NxgY/P8qv4PehJ3qfZDfW4HwQ/uSNLF SO5irDbKFTLjuwkrCMMdtgUjo/xb1StQ14ri1Bxv1UkA/bIwjVqyt+gMUVpvegQ+Peff qG4EAibX1FxdFxy8A92f6uSiv92YFS5FM3PH+5SGqa7OLIVqu/yGOPBW3106ZA1Dj0nN or6T2UMyGk7jCA89uhNo+9K4YwS8Q70+I2BoLGhEhoS19d02r0QG25cSU+dfJA25+76c lyFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jQW21UMpMMT39kQGkUZ44Bi2KAiI76Uffz4R9s7ZIY4=; b=XawdXNDNiiIuX+ymI08p49Quae3LrqBEpi+0xzqrXWHD4BuMxnL2hdOWumuGEbN1tn yFGCgV+L88JDQIJRq/wZofa6hfKN9XrYdj7Mj1ujLUn26yr1yRWYhScPe9idg2I0CRiU fnJJ3Y7mpY9eW7lmRm5HUaYKYfB3esGlioyVPQfqxt1axwa555MIFbRqycBLnvt6ICE6 xgytyCv6NwwyVAsDDa/gAvVYpw7OCuwhvoOGXHHozKgrGnayKToa36Asorw5CxYgjU9v dvKZ3o5xkxr+aV15WjZfnrWKE0BN2moUReTVm7PjkPFqZMIiVtLp2Wbgr2EY6EtJZWT6 fgpA== X-Gm-Message-State: ANoB5plDxj6R0rIP0SCKQWI5DKaSeXDyRuxSPiWIKJ/zkcul+3ERHK4G SsHylPh/KcBlI+cLhVyt73an X-Google-Smtp-Source: AA0mqf5ljrSPGVNBRtykID1TL3/cGOrewa2yjiZmVTTVZrWsBIkuV1+BoJ27rIUb9wyuYvjPhd49vw== X-Received: by 2002:a17:90a:d811:b0:213:aa8:dda with SMTP id a17-20020a17090ad81100b002130aa80ddamr30077911pjv.111.1669189815878; Tue, 22 Nov 2022 23:50:15 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:50:15 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 17/20] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Date: Wed, 23 Nov 2022 13:18:23 +0530 Message-Id: <20221123074826.95369-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the preparation of adding support for new gears, let's move the logic that finds the gear for each platform to a new function. This helps with code readability and also allows the logic to be used in other places of the driver in future. While at it, let's make it clear that this driver only supports symmetric gear setting (hs_tx_gear =3D=3D hs_rx_gear). Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 38e2ed749d75..919b6eae439d 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -278,6 +278,25 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) return 0; } =20 +static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + + if (host->hw_ver.major =3D=3D 0x1) { + /* + * HS-G3 operations may not reliably work on legacy QCOM + * UFS host controller hardware even though capability + * exchange during link startup phase may end up + * negotiating maximum supported gear as G3. + * Hence downgrade the maximum supported gear to HS-G2. + */ + return UFS_HS_G2; + } + + /* Default is HS-G3 */ + return UFS_HS_G3; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); @@ -692,19 +711,8 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *= hba, ufshcd_init_pwr_dev_param(&ufs_qcom_cap); ufs_qcom_cap.hs_rate =3D UFS_QCOM_LIMIT_HS_RATE; =20 - if (host->hw_ver.major =3D=3D 0x1) { - /* - * HS-G3 operations may not reliably work on legacy QCOM - * UFS host controller hardware even though capability - * exchange during link startup phase may end up - * negotiating maximum supported gear as G3. - * Hence downgrade the maximum supported gear to HS-G2. - */ - if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_tx_gear =3D UFS_HS_G2; - if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_rx_gear =3D UFS_HS_G2; - } + /* This driver only supports symmetic gear setting i.e., hs_tx_gear =3D= =3D hs_rx_gear */ + ufs_qcom_cap.hs_tx_gear =3D ufs_qcom_cap.hs_rx_gear =3D ufs_qcom_get_hs_= gear(hba); =20 ret =3D ufshcd_get_pwr_dev_param(&ufs_qcom_cap, dev_max_params, --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59F95C4332F for ; Wed, 23 Nov 2022 07:52:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236426AbiKWHwO (ORCPT ); Wed, 23 Nov 2022 02:52:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236400AbiKWHvZ (ORCPT ); Wed, 23 Nov 2022 02:51:25 -0500 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 805ABFBA83 for ; Tue, 22 Nov 2022 23:50:22 -0800 (PST) Received: by mail-pf1-x42c.google.com with SMTP id z26so16632836pff.1 for ; Tue, 22 Nov 2022 23:50:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uk4luKF8t4ifNKen4Qh4OvqAisGjZ8ae5pMGODayTWw=; b=N1BMzP3fnBp21+uZE5n+zjSk0+TSsCpwu5IpNglZVltoxGRcxfpfcbSvJZZOCYzYYU MU33WkMY5G5+DhTvFjV33dZxuRamOZBvMb5NnUQhwFgJngDpVKCJSSnvkZSyh/kngO6h Af9KAy+nR4p+Oo3t9F+oOWzAHqqABmJU9rYDk4sDmmnFY6407EypqeTse8Qyg/CN9FEF EBWtK9Gs6V7zVZZLfEz3NwhRri9b7imRhmWhGK92azUzhW6dDsI6tIQrc+8w22Jl4NHp 3ANXIrkn0dCsvDgr62uVoAeD+kSVVwCwLhyoldmuGmPvG1rLZbGhYZGemkuY0SN6rV7n WUww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uk4luKF8t4ifNKen4Qh4OvqAisGjZ8ae5pMGODayTWw=; b=zBu3mKPl1hi1oPs3JytYqlg6XQ9Nuy+5VcGGxKxD/guAhQqSJsCeGatq8nsH4XuEci kxJvn2EmEflee3V8wZXV5t9+9pyQS+CH9nmlQJ7supXjJH7xL+T6ywfCa8Gqo6PgAWij lObjlvZk89ELNqEHb86Sr2lfRtiDL7cDan5nVfsHWRUq9mxXUE20WvPj29+rCDazWOCl dZ+2eDIHcXlwFUWSnIazKZWWvUpILSJtF+CQo3h0853mtvXjtTiOlro0Ciy47JSnPtsg Xsyk6jZADLc0sBxz7ZjtXW1tHO3wMeI4JIPR+TF2ZbkmhE/72Q4CeZEM0U/nMNhwWCg7 PblA== X-Gm-Message-State: ANoB5pnCPLI7tLYKvFmgpSoTb3B5qWSJAgLrTzBNGN+sYH73Lfc6MLWG B5xusoBz8KDGqq4D4sFc1YmG X-Google-Smtp-Source: AA0mqf7da5sZKLT7s6i7zvfLHItWQvjLOdsAyHCV2RWyrTZWvAw7Fd7hnX8C7gpDI3NKE4LSFwDrdA== X-Received: by 2002:a63:d712:0:b0:470:4522:f317 with SMTP id d18-20020a63d712000000b004704522f317mr14809770pgg.129.1669189821982; Tue, 22 Nov 2022 23:50:21 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:50:21 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 18/20] scsi: ufs: ufs-qcom: Add support for reinitializing the UFS device Date: Wed, 23 Nov 2022 13:18:24 +0530 Message-Id: <20221123074826.95369-19-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting from Qualcomm UFS version 4, the UFS device needs to be reinitialized after switching to maximum gear by the UFS core. Hence, add support for it by enabling the UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH quirk, implementing reinit_notify() callback and using the agreed gear speed for setting the PHY mode. Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 26 ++++++++++++++++++++++---- drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 919b6eae439d..3efef2f36e69 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -302,7 +302,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct phy *phy =3D host->generic_phy; int ret; - bool is_rate_B =3D UFS_QCOM_LIMIT_HS_RATE =3D=3D PA_HS_MODE_B; =20 /* Reset UFS Host Controller and PHY */ ret =3D ufs_qcom_host_reset(hba); @@ -310,9 +309,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) dev_warn(hba->dev, "%s: host reset returned %d\n", __func__, ret); =20 - if (is_rate_B) - phy_set_mode(phy, PHY_MODE_UFS_HS_B); - /* phy initialization - calibrate the phy */ ret =3D phy_init(phy); if (ret) { @@ -321,6 +317,8 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) return ret; } =20 + phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); + /* power on phy - start serdes and phy's power and clocks */ ret =3D phy_power_on(phy); if (ret) { @@ -723,6 +721,9 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, return ret; } =20 + /* Use the agreed gear */ + host->hs_gear =3D dev_req_params->gear_tx; + /* enable the device ref clock before changing to HS mode */ if (!ufshcd_is_hs_mode(&hba->pwr_info) && ufshcd_is_hs_mode(dev_req_params)) @@ -836,6 +837,9 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *h= ba) | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); } + + if (host->hw_ver.major > 0x3) + hba->quirks |=3D UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; } =20 static void ufs_qcom_set_caps(struct ufs_hba *hba) @@ -1044,6 +1048,12 @@ static int ufs_qcom_init(struct ufs_hba *hba) dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); =20 + /* + * Power up the PHY using the minimum supported gear (UFS_HS_G2). + * Switching to max gear will be performed during reinit if supported. + */ + host->hs_gear =3D UFS_HS_G2; + return 0; =20 out_variant_clear: @@ -1410,6 +1420,13 @@ static void ufs_qcom_config_scaling_param(struct ufs= _hba *hba, } #endif =20 +static void ufs_qcom_reinit_notify(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + + phy_power_off(host->generic_phy); +} + /* * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1433,6 +1450,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_= vops =3D { .device_reset =3D ufs_qcom_device_reset, .config_scaling_param =3D ufs_qcom_config_scaling_param, .program_key =3D ufs_qcom_ice_program_key, + .reinit_notify =3D ufs_qcom_reinit_notify, }; =20 /** diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 7fe928b82753..4b00c67e9d7f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -217,6 +217,8 @@ struct ufs_qcom_host { struct reset_controller_dev rcdev; =20 struct gpio_desc *device_reset; + + u32 hs_gear; }; =20 static inline u32 --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A9EAC4332F for ; Wed, 23 Nov 2022 07:52:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235771AbiKWHwV (ORCPT ); Wed, 23 Nov 2022 02:52:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236406AbiKWHv1 (ORCPT ); Wed, 23 Nov 2022 02:51:27 -0500 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5853DFBAAC for ; Tue, 22 Nov 2022 23:50:28 -0800 (PST) Received: by mail-pg1-x530.google.com with SMTP id 62so16063948pgb.13 for ; Tue, 22 Nov 2022 23:50:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=glMEmrKRq4os3IrGzZuvFW519vUHu5A1N8n6PQVGzlQ=; b=BOIqJRhDIjAKXMdP0E72f+a3Mm553ME26QYgvjzRlnw5V6BDIRXLMaF1se86tGbYQB ZKJSBLv7ClSBzIHeOGPty5hmKbwaBrkAZyu5V7cAXRjG5/gkyz6zJVwZsudzNbC9l4sX xGxB/hxYu0PBYiO+yoCyjYeMiJMGg99bn5EY+aEng7GPz83FRjYFs/kI3QkayzRoFvhW wfs9iSr4xEj+gPjd1lE6V0ENFCIGqFFvmzEws69pHbHcVtxSZqsQQo4soZY0JUzY4sMe KDFqmpqix67JN0Z5Q/X7RLjj2iVbNpbHIil8wCaS62qxF0o21h88N9YOigHsix7vCpN1 62LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=glMEmrKRq4os3IrGzZuvFW519vUHu5A1N8n6PQVGzlQ=; b=76pRlo23PA1x+2f7TPyGoeQFZ/r11kAO2faWmzC4BVHgAX/PAU/cgEg00grhH0vcJK EpxK2zQhKa9z4qbMUANPu1gWdSV3hq/Q6MNYo3mm09iMWNw79SZuT+Tg1xtk33d2jMVj qpP3+ud8g06mobGUBQAcmsUnhYHAb2qLFqFB4c/WWe/lVeIk8V+J1SiauZ2G5/8GYifT K9lRwBJbIA2u9AGyd4lBQli8zX2z3vw7ePGsgDa8K16VzTVGKNK9fqiqFIEuBU6mX1rD Aufml0jT5wbnbybvkmmEmwLdNsLntjuRZBbgJUOGrdxGt300n9binyGDuTnw16ozWlD7 9Zag== X-Gm-Message-State: ANoB5pndQcmLKJmNMTzzpa22LC/v8SJWIFnNJp2mGA7Hp5j1XD0F/d0z tJ5rNLGJIklWDT4biIcLU1fX X-Google-Smtp-Source: AA0mqf6lPAF5IEkGpX+K2Q9GKm/yZZjproyXopeEaYdMDy/lg31urXcP7Dnn38GSLO1N23qo/ycyeA== X-Received: by 2002:a63:5359:0:b0:46f:3dfb:87e1 with SMTP id t25-20020a635359000000b0046f3dfb87e1mr9010367pgl.290.1669189827640; Tue, 22 Nov 2022 23:50:27 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.50.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:50:26 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 19/20] scsi: ufs: ufs-qcom: Add support for finding max gear on new platforms Date: Wed, 23 Nov 2022 13:18:25 +0530 Message-Id: <20221123074826.95369-20-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting from Qcom UFS version 4.0, vendor specific REG_UFS_PARAM0 register can be used to determine the maximum gear supported by the controller. Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 2 ++ drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 3efef2f36e69..607fddb7b4c3 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -291,6 +291,8 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) * Hence downgrade the maximum supported gear to HS-G2. */ return UFS_HS_G2; + } else if (host->hw_ver.major >=3D 0x4) { + return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); } =20 /* Default is HS-G3 */ diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 4b00c67e9d7f..dd3abd23ec22 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -94,6 +94,10 @@ enum { #define TMRLUT_HW_CGC_EN BIT(6) #define OCSC_HW_CGC_EN BIT(7) =20 +/* bit definitions for REG_UFS_PARAM0 */ +#define MAX_HS_GEAR_MASK GENMASK(6, 4) +#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) + /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 b= its wide */ =20 --=20 2.25.1 From nobody Thu Apr 16 02:22:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F3FCC433FE for ; Wed, 23 Nov 2022 07:52:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236439AbiKWHw4 (ORCPT ); Wed, 23 Nov 2022 02:52:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236339AbiKWHvj (ORCPT ); Wed, 23 Nov 2022 02:51:39 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C4FBFBABE for ; Tue, 22 Nov 2022 23:50:34 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id t17so14562479pjo.3 for ; Tue, 22 Nov 2022 23:50:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6pljquG0hkdcBPdXIDtkq1v6aN8iyQB1w4S/2qg/cek=; b=riPHLLSPLvU4P+d6u9OTtrSXJONvT4DAWehSTt8MlAkRICfZiHBToxi4kDEWfviIsZ h4GppwDuuDtXzzjSle39EzY+sWR9P2DfAoziF1MiznuN458awUnLiX/RsQVdSjhwa9Ms N7ygqjsasMBdsGnhMbFuz8KQKDG3sgS/nb0h0LVdwiKMu8JgiDY8oI8doDST/Z72ZCYT tOmvkb6tOyXbn1sYrt5J6aXGX7NYMQ5KuIDCIMqYJRE/bssq6GURpxVq7JGlg2buknlK VWlCBZ2geenSJVXVHz6jVyyq2m82Ua+nFlNCMkC42mjSdkzzVQp3p4YoKphWcZ+5LkHO vXWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6pljquG0hkdcBPdXIDtkq1v6aN8iyQB1w4S/2qg/cek=; b=cESBxwZMy3PgKJS/FoouFRmPVhn1DiIbUrl/+WhD348S0x54R2wQABKeq0YnKQi2/a SlrTrwXwzZlH3kJKxqCCBYPDXrgSRwiN+dy27ePezwBcRXeKzksomQEB3XxezOi36vcz hoJB8xhM/MUrgYSuwp0kriRzUiObVSzkmaXBs3j0sqybkHkFUpdLNQnvpuHUA/ffYgkl Tw63b/EBCrvcxWxBdaEsv9z2XxfnscW8slCE23MF3k4lH0w2V+u1gQTU5l3v+DQduMac kFmrj+nv8kEsh2lCdTY7QQ9Bf7k+OmdyIFUGS0Wr7Wpvr/PKs/LKZ+2el8CcOmO6CZ8s mxkQ== X-Gm-Message-State: ANoB5pnFaQxG4nInGm1jY8OJsw4QVUmkuho2VnOnp0bWFoh7pbT3sVBU bBybjLfLjgP5E7ELfYStya3u X-Google-Smtp-Source: AA0mqf4oJohuIJiFaMQ1NxpUqgruyQRg1aKK4w0wEW+uEmRdgL4uVGadHWpYVlHujlCe+RkwM2jNBQ== X-Received: by 2002:a17:90a:307:b0:213:ff80:b37f with SMTP id 7-20020a17090a030700b00213ff80b37fmr35775172pje.118.1669189833465; Tue, 22 Nov 2022 23:50:33 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.50.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:50:32 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 20/20] MAINTAINERS: Add myself as the maintainer for Qcom UFS driver Date: Wed, 23 Nov 2022 13:18:26 +0530 Message-Id: <20221123074826.95369-21-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom UFS driver has been left un-maintained till now. I'd like to step up to maintain the driver and its binding. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf0f18502372..149fd6daf52b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21097,6 +21097,14 @@ L: linux-mediatek@lists.infradead.org (moderated f= or non-subscribers) S: Maintained F: drivers/ufs/host/ufs-mediatek* =20 +UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER QUALCOMM HOOKS +M: Manivannan Sadhasivam +L: linux-arm-msm@vger.kernel.org +L: linux-scsi@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +F: drivers/ufs/host/ufs-qcom.c + UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER RENESAS HOOKS M: Yoshihiro Shimoda L: linux-renesas-soc@vger.kernel.org --=20 2.25.1