From nobody Wed Apr 15 23:29:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15DEFC4332F for ; Tue, 22 Nov 2022 10:16:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232931AbiKVKQn (ORCPT ); Tue, 22 Nov 2022 05:16:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232739AbiKVKQd (ORCPT ); Tue, 22 Nov 2022 05:16:33 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9454E528BE; Tue, 22 Nov 2022 02:16:32 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGQPJ008103; Tue, 22 Nov 2022 04:16:26 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669112186; bh=Z7PmexFMzjsMKq/hM3kpC78Li0Ya2z8I4QF30Hq1gkQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=H4iic0793Mjgy3XymWMdqV/Xufj+ZMALa7l6tdSRs0YGwHXF9sozTIbHI3/sJq9W9 ZstPW0VB3Mji3xPMyCEusqJJbWSm3Pjk506B7GXPytRDUvdxZ3hKyDgt8bOAvt1M/3 w5qSvkxni1Nx0+z2Wpei2fLz1EeP6f0U+Cbr4scs= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AMAGQBY079473 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Nov 2022 04:16:26 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:25 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:25 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGM9h088710; Tue, 22 Nov 2022 04:16:24 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB Date: Tue, 22 Nov 2022 02:16:09 -0800 Message-ID: <20221122101616.770050-2-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for single instance of USB 3.0 controller in J721S2 SoC. Reviewed-by: Ravi Gunasekaran Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 8915132efcc1..b4869bff4f22 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -26,6 +26,20 @@ l3cache-sram@200000 { }; }; =20 + scm_conf: syscon@104000 { + compatible =3D "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg =3D <0x00 0x00104000 0x00 0x18000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller-0 { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + }; + gic500: interrupt-controller@1800000 { compatible =3D "arm,gic-v3"; #address-cells =3D <2>; @@ -745,6 +759,34 @@ cpts@310d0000 { }; }; =20 + usbss0: cdns-usb@4104000 { + compatible =3D "ti,j721e-usb"; + reg =3D <0x00 0x04104000 0x00 0x100>; + clocks =3D <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names =3D "ref", "lpm"; + assigned-clocks =3D <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents =3D <&k3_clks 360 17>; + power-domains =3D <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-coherent; + + usb0: usb@6000000 { + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D , + , + ; + interrupt-names =3D "host", "peripheral", "otg"; + maximum-speed =3D "super-speed"; + dr_mode =3D "otg"; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.38.GIT From nobody Wed Apr 15 23:29:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95848C433FE for ; Tue, 22 Nov 2022 10:17:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232882AbiKVKR3 (ORCPT ); Tue, 22 Nov 2022 05:17:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232934AbiKVKQv (ORCPT ); Tue, 22 Nov 2022 05:16:51 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F39AC54B38; Tue, 22 Nov 2022 02:16:38 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGVUb095995; Tue, 22 Nov 2022 04:16:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669112191; bh=aP3WJxdmh6Lz7lDEVBUKu4BJt1bFVAwOK3NP7I/9rR0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uTdwXwu/VF9Sq6hGnIEfogbb6YlBPTXYOQnFbaLxfQpXZmqvjRfG5KUXk3lAxNM1r FeDT48f72lkXcV7/FN9i1BxnHyj333b2JgA6wJ3pBkAP4FULaKkoOuIlfeOmy1KayN UPrPV3gTp6m5IoeESWRHOs3H/aY04sVzzpybdW9c= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AMAGVOL079489 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Nov 2022 04:16:31 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:30 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:30 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGRRL088764; Tue, 22 Nov 2022 04:16:29 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Date: Tue, 22 Nov 2022 02:16:10 -0800 Message-ID: <20221122101616.770050-3-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by: Matt Ranostay Reviewed-by: Ravi Gunasekaran --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index b4869bff4f22..2858ba589d54 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ =20 +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; @@ -38,6 +49,13 @@ usb_serdes_mux: mux-controller-0 { #mux-control-cells =3D <1>; mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + + serdes_ln_ctrl: mux-controller-80 { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; }; =20 gic500: interrupt-controller@1800000 { @@ -787,6 +805,42 @@ usb0: usb@6000000 { }; }; =20 + serdes_wiz0: wiz@5060000 { + compatible =3D "ti,j721s2-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks =3D <&k3_clks 365 3>; + assigned-clock-parents =3D <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05060000 0x00010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.38.GIT From nobody Wed Apr 15 23:29:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 356D5C43219 for ; Tue, 22 Nov 2022 10:17:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233023AbiKVKRc (ORCPT ); Tue, 22 Nov 2022 05:17:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233040AbiKVKQy (ORCPT ); Tue, 22 Nov 2022 05:16:54 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6B01554D6; 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Tue, 22 Nov 2022 04:16:35 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGWqL030012; Tue, 22 Nov 2022 04:16:34 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Date: Tue, 22 Nov 2022 02:16:11 -0800 Message-ID: <20221122101616.770050-4-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for two instance of OSPI in J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Reviewed-by: Vaishnav Achath --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..a588ab8d867b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -306,4 +306,44 @@ cpts@3d000 { ti,cpts-periodic-outputs =3D <2>; }; }; + + fss: syscon@47000000 { + compatible =3D "simple-bus"; + reg =3D <0x00 0x47000000 0x00 0x100>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ospi0: spi@47040000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47040000 0x00 0x100>, + <0x5 0x0000000 0x1 0x0000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 109 5>; + assigned-clocks =3D <&k3_clks 109 5>; + assigned-clock-parents =3D <&k3_clks 109 7>; + assigned-clock-rates =3D <166666666>; + power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + ospi1: spi@47050000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47050000 0x00 0x100>, + <0x7 0x0000000 0x1 0x0000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 110 5>; + power-domains =3D <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + }; }; --=20 2.38.GIT From nobody Wed Apr 15 23:29:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3193C433FE for ; Tue, 22 Nov 2022 10:17:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233095AbiKVKRf (ORCPT ); Tue, 22 Nov 2022 05:17:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233161AbiKVKQ4 (ORCPT ); Tue, 22 Nov 2022 05:16:56 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E937C56540; Tue, 22 Nov 2022 02:16:45 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGerc116927; Tue, 22 Nov 2022 04:16:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669112200; bh=O161wI64MkqL1bXQrEKXqqHqqSz8Rg1odY1/d9cyRhc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iE6yi9OPjfMSL/QeaNvw2OsHPBeW8UCSkjgzm3zAqQW9cQleFR+RoinztIc3WotI0 5omkiInNyiSiMAtnjJ1B9NNFWfGcGwSasWEnRzBX2QHPQfutYP4cyyugRuElAAU6Wa h92lkTysL4su7tAiPjbESnzj5x4kXpu48dNRs+8A= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AMAGeHQ057008 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Nov 2022 04:16:40 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:40 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:40 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGbrI030043; Tue, 22 Nov 2022 04:16:39 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Date: Tue, 22 Nov 2022 02:16:12 -0800 Message-ID: <20221122101616.770050-5-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Reviewed-by: Ravi Gunasekaran Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay --- .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..c3a397484c70 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ =20 #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include =20 / { compatible =3D "ti,j721s2-evm", "ti,j721s2"; @@ -296,6 +299,25 @@ &cpsw_port1 { phy-handle =3D <&phy0>; }; =20 +&serdes_ln_ctrl { + idle-states =3D , , + , ; +}; + +&serdes_refclk { + clock-frequency =3D <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.38.GIT From nobody Wed Apr 15 23:29:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1795C4332F for ; Tue, 22 Nov 2022 10:17:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233219AbiKVKRk (ORCPT ); Tue, 22 Nov 2022 05:17:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233399AbiKVKRA (ORCPT ); Tue, 22 Nov 2022 05:17:00 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84AAB51328; Tue, 22 Nov 2022 02:16:51 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGjG0118385; Tue, 22 Nov 2022 04:16:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669112205; bh=ac4Z8P3rBXZkZq+HC3t7a6d1XGYyHS+dBSY/4gN4278=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=twiD3GSeMPrLYlxSLVLnkzZvQqvferS+enX6t48JadDlVZDVLLWwdc00VW/fKz/NN 7Uw7pE27vX8EZhrrhr8574EFGPSMFiBzozW2Z7+g96fk51idRspgKDpFQprT7mtxS+ qFmkMQ3DzdC1b7PD8XyNvskpme+G6Raf3uAxDEMg= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AMAGjm2019851 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Nov 2022 04:16:45 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:45 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:44 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGg5t030109; Tue, 22 Nov 2022 04:16:43 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Date: Tue, 22 Nov 2022 02:16:13 -0800 Message-ID: <20221122101616.770050-6-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Reviewed-by: Ravi Gunasekaran Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay --- .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c3a397484c70..c787d46f89de 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; =20 &wkup_pmx0 { @@ -318,6 +324,22 @@ serdes0_pcie_link: phy@0 { }; }; =20 +&usb_serdes_mux { + idle-states =3D <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + pinctrl-0 =3D <&main_usbss0_pins_default>; + pinctrl-names =3D "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode =3D "otg"; + maximum-speed =3D "high-speed"; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.38.GIT From nobody Wed Apr 15 23:29:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70662C4332F for ; Tue, 22 Nov 2022 10:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233427AbiKVKRp (ORCPT ); Tue, 22 Nov 2022 05:17:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233489AbiKVKRE (ORCPT ); Tue, 22 Nov 2022 05:17:04 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 918A854B25; Tue, 22 Nov 2022 02:16:55 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGoih096025; Tue, 22 Nov 2022 04:16:50 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669112210; bh=664ekDjiGwxoAdpJEQPqESRVJIF1G47RriN6f9uEIx4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sZzbImbHgdaolLmqKI77wQoMGQ0q6QqyBlzhwlm9999KjTeKBtmYLJCUECjLns0R1 rINN4x1joRTCYxmJyMQlRVC8o7s5Ds0v02THNPKC1M31+LbHeipGp8VQ1Dj+ArnecX IQ2pAKAdANvhIo7q+reoKOsHLDI648gH3jcLyZJE= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AMAGokl017906 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Nov 2022 04:16:50 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:49 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:49 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGkHN088950; Tue, 22 Nov 2022 04:16:48 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Date: Tue, 22 Nov 2022 02:16:14 -0800 Message-ID: <20221122101616.770050-7-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Reviewed-by: Vaishnav Achath --- .../dts/ti/k3-j721s2-common-proc-board.dts | 34 +++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c787d46f89de..0503e690cfaf 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -206,6 +206,20 @@ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-defau= lt { J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; =20 &main_gpio2 { @@ -340,6 +354,26 @@ &usb0 { maximum-speed =3D "high-speed"; }; =20 +&ospi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <40000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a..2ffea00e19d7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,6 +39,28 @@ transceiver0: can-phy0 { }; }; =20 +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins =3D < @@ -79,3 +101,23 @@ &main_mcan16 { pinctrl-names =3D "default"; phys =3D <&transceiver0>; }; + +&ospi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; --=20 2.38.GIT From nobody Wed Apr 15 23:29:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76DAEC43219 for ; Tue, 22 Nov 2022 10:17:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232394AbiKVKRv (ORCPT ); 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Tue, 22 Nov 2022 04:16:54 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:54 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:54 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGp5Q088978; Tue, 22 Nov 2022 04:16:53 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Date: Tue, 22 Nov 2022 02:16:15 -0800 Message-ID: <20221122101616.770050-8-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add PCIe1 RC device tree node for the single PCIe instance present on the j721s2. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 2858ba589d54..27631ef32bf5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -841,6 +841,47 @@ serdes0: serdes@5060000 { }; }; =20 + pcie1_rc: pcie@2910000 { + compatible =3D "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb013>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.38.GIT From nobody Wed Apr 15 23:29:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 145BCC433FE for ; Tue, 22 Nov 2022 10:17:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233487AbiKVKRz (ORCPT ); Tue, 22 Nov 2022 05:17:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233522AbiKVKRH (ORCPT ); Tue, 22 Nov 2022 05:17:07 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C1FD554D6; Tue, 22 Nov 2022 02:17:03 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGx7d096045; Tue, 22 Nov 2022 04:16:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669112219; bh=cN2rqEsmXZ3LoONcfjQ9oRQd9dmNmx7VWNhQa5s4nMQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qMoBQ3A5gutUxye5sZgifXP12FkJVMXlFleeEMFHbiMvvpsaBecI2Y6W30TRdc5ET vFB1NIv9clqbs9bcbNlbcnwp24WNaygv6y5itflvBfBYRYXo+x2RftVMVSppCE33CY V260ZHSgNcWpCi4NH05Q9sgZZpffmHS8rFV2bfDE= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AMAGx0C079817 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Nov 2022 04:16:59 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:58 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:58 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGuUm089004; Tue, 22 Nov 2022 04:16:57 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Tue, 22 Nov 2022 02:16:16 -0800 Message-ID: <20221122101616.770050-9-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 0503e690cfaf..561d70cdee9b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -374,6 +374,13 @@ flash@0{ }; }; =20 +&pcie1_rc { + reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + num-lanes =3D <1>; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.38.GIT