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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id w9-20020a05600018c900b002c5a1bd5280sm12434670wrq.95.2023.03.07.04.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 04:41:16 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 13:41:07 +0100 Subject: [PATCH v4 1/2] arm64: dts: mediatek: add i2c support for mt8365 SoC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221122-mt8365-i2c-support-v4-1-885ad3301d5a@baylibre.com> References: <20221122-mt8365-i2c-support-v4-0-885ad3301d5a@baylibre.com> In-Reply-To: <20221122-mt8365-i2c-support-v4-0-885ad3301d5a@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Qii Wang , Matthias Brugger Cc: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno , devicetree@vger.kernel.org, Alexandre Mergnat , Fabien Parent , Rob Herring , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2699; i=amergnat@baylibre.com; h=from:subject:message-id; bh=u+MtjyWPgh4jPQn4QvtpwirJ4T/DfAOJHsOpg52IJ9U=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkBzDqCiWuVUZenZTJHFBYtVy0B5IyQnJXC+uVZ9IP OirqWTuJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAcw6gAKCRArRkmdfjHURT4AD/ 9wYMx1vHjoOrKmlL7xjPDPSTvpxLJZf/NXsVj37zs7wt+ueBvxUem49Dxy1ChEA0UEip6Tt0x8r4tR Kd7nC8peqX2AoLfK7HFkiQ1QL8y1r1WC/IRQZofDQAwri2iN2TcTCaxKBiRttPQikbRycbw6xoR1Rq YvotJdmNGUOzxpi0lIURHfkWFSBG/2eNJRAr5cRXrxv1PkgXl7nGSNSNQU10P2pkXTA3+oE2FqxizR GGQNhUqN0PSzwnC3PsZomQgFCLnh+jj+yWgk3Ju6jSiDPdWFMYygAH7XiFtSNH6FrlODYqSDUZbiaC w3rRYdc25p47Q5W9d48jNpVvVguNx793pdG1Xqig5iYkGOID8+dJkza1mqQDSU/DB+R7PHt2WWxSNu kZlpVXSqgijHOqbYEE9jiKLSClpqHuKE10iODGIaYpQfVpCiNXNf+Ejz+iWdvuxguul+ta23esEnMU DVx9B5rcigh3xVI3nUOfybn8GqU+MCjHma5+m/bLOmIMHA4Ih3dh6PwT+laGOen53v/mH+jN9R1mLu XRcnvzSsk9v+FSW0b+yMeR8+6+mo4kRxtMhSbFho1HDCtbDdtGhcTf3fbHuI9/CfwNwnbAZgwnObPp bcLHAx37v+aHN4V1Q4UX8jT4Xe4WFNMj0yiu90hzQaqkKmUG//rn7BJlxAvg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are four I2C master channels in MT8365 with a same HW architecture. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 48 ++++++++++++++++++++++++++++= ++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi index 15ac4c1f0966..b70f4d256f63 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -282,6 +282,42 @@ pwm: pwm@11006000 { clock-names =3D "top", "main", "pwm1", "pwm2", "pwm3"; }; =20 + i2c0: i2c@11007000 { + compatible =3D "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg =3D <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@11008000 { + compatible =3D "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg =3D <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@11009000 { + compatible =3D "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg =3D <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + spi: spi@1100a000 { compatible =3D "mediatek,mt8365-spi", "mediatek,mt7622-spi"; reg =3D <0 0x1100a000 0 0x100>; @@ -295,6 +331,18 @@ spi: spi@1100a000 { status =3D "disabled"; }; =20 + i2c3: i2c@1100f000 { + compatible =3D "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg =3D <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + ssusb: usb@11201000 { compatible =3D "mediatek,mt8365-mtu3", "mediatek,mtu3"; reg =3D <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; --=20 b4 0.10.1 From nobody Sun Nov 10 20:43:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7746BC678D5 for ; Tue, 7 Mar 2023 12:41:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230100AbjCGMld (ORCPT ); Tue, 7 Mar 2023 07:41:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229758AbjCGMlW (ORCPT ); Tue, 7 Mar 2023 07:41:22 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 664667C3E1 for ; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id w9-20020a05600018c900b002c5a1bd5280sm12434670wrq.95.2023.03.07.04.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 04:41:17 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 13:41:08 +0100 Subject: [PATCH v4 2/2] arm64: dts: mediatek: enable i2c0 for mt8365-evk board MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221122-mt8365-i2c-support-v4-2-885ad3301d5a@baylibre.com> References: <20221122-mt8365-i2c-support-v4-0-885ad3301d5a@baylibre.com> In-Reply-To: <20221122-mt8365-i2c-support-v4-0-885ad3301d5a@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Qii Wang , Matthias Brugger Cc: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno , devicetree@vger.kernel.org, Alexandre Mergnat , Fabien Parent , Rob Herring , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1291; i=amergnat@baylibre.com; h=from:subject:message-id; bh=/2/cjSO2mF7U+slihZOD76PFWiM0Jv1Qz+ElLd/bOnw=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkBzDqcQGDX7mF+2FUnSGPLDJyNAnKOn4NaJfOwzgl MmtGUVSJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAcw6gAKCRArRkmdfjHURYkYD/ 9KfGHtkTIXYn298xwf9hQ8ovbQgNJm4iLoD0gTwEbNJbtAQWcm+pf/kgA5UzVtT6LolXsRv6xkDDFg HtHgOj/0G6IQrF9O3BuUX7c1MW5ynG/CTjXxf/uYzlDG95t7NAQIxy7MzHKMlDur6zTNmVrks7GI5z s9EDsvMqQx1j+LBOv1Jj0Moq6vzCXrP4+LucyqXzSg7hMmXn7mRFalNAd+TJpN295ZFwwmL3Qg3EQs UnAuqUywmHwMWYxwRm9fFKutfibO2LvXfmQOs1Mgo+9NpQfuQxmtenzmqwqcvAyW0qhU/Ai8GFd5Wz w9/2JIXAN4K3kquecBWSkFZNGfux0VlX63Womo8TbX1mDWq3TNvNeH5g7mdqKdkccBF8XU2F7K/+5L 3s/7x3JaCafJg1A/ckS5I1+eeDleUiHGtk5ZNYYEWNTMJdi64+G3bhL6OeU1DZdCx/ACZJv+Qgn4ta HMdFJgqwFGG3qnM0TxbgjGoGFtYn1E1Y8DI1BNhHugJHGg/Em9usE2p/nZxShBJrRbM7VGxaMWb5Wh 2UsHNmnXEA8Qnu+FIL/w4Bi4o6PQw+AVgHrBxdDRscOaCeMd6axkQWAmFEsTSCiG7cMtwj+oAcSlI7 IYdbwUpMSrB7sIeFan52LlY4xfCjYz/+APqYAGG9BpSyF31DoOnVHpqvrHAg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable the I2C0 bus provides communication with: - The integrated RT9466 Switching Battery Charger. - The integrated MT6691 LP4X buck for VDDQ. - The integrated MT6691 LP4X buck for VDD2. - The pin header, to plug external I2C devices. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts index 4683704ea235..bfaee9a4a38b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -87,6 +87,13 @@ optee_reserved: optee@43200000 { }; }; =20 +&i2c0 { + clock-frequency =3D <100000>; + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + &pio { gpio_keys: gpio-keys-pins { pins { @@ -96,6 +103,16 @@ pins { }; }; =20 + i2c0_pins: i2c0-pins { + pins { + bias-pull-up; + mediatek,drive-strength-adv =3D <0>; + mediatek,pull-up-adv =3D <3>; + pinmux =3D , + ; + }; + }; + uart0_pins: uart0-pins { pins { pinmux =3D , --=20 b4 0.10.1