From nobody Fri Dec 19 17:18:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FA39C4332F for ; Sat, 19 Nov 2022 04:10:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233578AbiKSEKc (ORCPT ); Fri, 18 Nov 2022 23:10:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231789AbiKSEJt (ORCPT ); Fri, 18 Nov 2022 23:09:49 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC7E174A99; Fri, 18 Nov 2022 20:09:48 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AJ49hCi028783; Fri, 18 Nov 2022 22:09:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1668830983; bh=BYL/GMzjP6vuyqmTQ9/yPWf3BAncE5bqZIl7zP3juDM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LULT6bBytXQOm59etv+OmG2/CZ5+iA+W9IUAaOMCrO2kb1hXi0K+d37ogjsUzUNoN 6YmW304Q9ajqVFEVECQibwJUC7eaHnrCcz7gg9/RbAdCwa8YZ9XXWC011gQ5TZWenB 89ZevVJkjNUIdzRQH5jOIalfcIbzfsqMgJNaaq7M= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AJ49h3Z067740 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Nov 2022 22:09:43 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 18 Nov 2022 22:09:43 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 18 Nov 2022 22:09:43 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AJ49eBg118853; Fri, 18 Nov 2022 22:09:42 -0600 From: Matt Ranostay To: , , , , , , CC: , , Subject: [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Date: Fri, 18 Nov 2022 20:09:05 -0800 Message-ID: <20221119040906.9495-8-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221119040906.9495-1-mranostay@ti.com> References: <20221119040906.9495-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add PCIe device tree node (both RC and EP) for the single PCIe instance present in j721s2. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index adbb172658b9..04294e25d587 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -841,6 +841,67 @@ serdes0: serdes@5060000 { }; }; =20 + pcie1_rc: pcie@2910000 { + compatible =3D "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb013>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.38.GIT