From nobody Fri Dec 19 19:00:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24BC4C4332F for ; Fri, 18 Nov 2022 14:15:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242254AbiKROPV (ORCPT ); Fri, 18 Nov 2022 09:15:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242216AbiKROPM (ORCPT ); Fri, 18 Nov 2022 09:15:12 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27DB266C9C; Fri, 18 Nov 2022 06:15:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668780912; x=1700316912; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=18jsSFYGJy6gbnsbxxDweHKGvPhAtMZ4eTFHplPUl9k=; b=mfu4VgRdZBG0idDlssInTmD6n3wPVWo0NT2uAT/dMnHEg1mIJ2GK6dJk MNQb0fCQiHQHn2ka6reQvwx2B7Szng+aO8Aa95KcgAUaUkjoDc789E7vy mUfHnF33lpK6AnDCg4Q6IG0yCO83cVctLCvvKETspi5W0jjC+ihb4LiHK Rc2GkShALVKCDswZMRJWtCmWwMGw0sW3/UC8CsAzA9uI8YBxEcQIgN5Kq OK6MSD3DESyE5RGbIcKZ8WUYJjWAQnBCuHAhqEZy+QbC6Ip7G8i4db5fW u4qXfnUi1ABoSZ3zuH/BgqWUZUsVAv6GTcRf84dNR2tp2DkWdPp4WBtjC Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10535"; a="292842728" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="292842728" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 06:15:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10535"; a="673204436" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="673204436" Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga001.jf.intel.com with ESMTP; 18 Nov 2022 06:15:06 -0800 From: Jiaxi Chen To: kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com, ndesaulniers@google.com, alexandre.belloni@bootlin.com, peterz@infradead.org, jpoimboe@kernel.org, chang.seok.bae@intel.com, pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com, jmattson@google.com, sandipan.das@amd.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, fenghua.yu@intel.com, keescook@chromium.org, nathan@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/6] x86: KVM: Advertise CMPccXADD CPUID to user space Date: Fri, 18 Nov 2022 22:15:04 +0800 Message-Id: <20221118141509.489359-2-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221118141509.489359-1-jiaxi.chen@linux.intel.com> References: <20221118141509.489359-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CMPccXADD is a new set of instructions in the latest Intel platform Sierra Forest. This new instruction set includes a semaphore operation that can compare and add the operands if condition is met, which can improve database performance. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EAX[bit 7] This CPUID is exposed to userspace. Besides, there is no other VMX control for this instruction. Signed-off-by: Jiaxi Chen --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index b71f4f2ecdd5..19db3940f262 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +#define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructio= ns */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 62bc7a01cecc..7ab7cc717b1c 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -657,7 +657,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); =20 kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(AVX_VNNI) | F(AVX512_BF16) + F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) ); =20 kvm_cpu_cap_mask(CPUID_D_1_EAX, --=20 2.27.0