From nobody Fri Dec 19 20:15:53 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1FC6C433FE for ; Fri, 18 Nov 2022 13:32:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242121AbiKRNcs (ORCPT ); Fri, 18 Nov 2022 08:32:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242150AbiKRNcN (ORCPT ); Fri, 18 Nov 2022 08:32:13 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C14B8FB35 for ; Fri, 18 Nov 2022 05:32:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668778330; x=1700314330; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dJwBIFugX5v1sFvIYnUIgu60nhe9NDrxApRtl04GOC0=; b=DIeO/DLnyxUpjrXWvY/9Hjc3W38rgN6desmvf+UJkdbZDnR4tlbd8+96 eTkmiwcUzH5cJL/v1OpaVyq2SyVT1Pvs+X4tk0/ut3kBF6NamY807XTX0 2QZIe+beAg+P1Q6zRr32Qoz+9K5gblMZVZoYdEDblyTEBTP+IazuFyLQl TSoNtMxCmOoKhtMbqedy62rQjiG9MKLQVtdedj77DyWLY4uZlj9DLSLAe zkUBV7EoAFR5uqiQHJRYeRp0cfUrYD1UKAuB2lRgI2gtSPrlMjrPiQdGp SWCcpAb89GJOLAabwrX+NE0+20xYCTmaaE4IhlDcpLjIgKod8WG7ktpBE w==; X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="314285090" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="314285090" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 05:32:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="642511998" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="642511998" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga007.fm.intel.com with ESMTP; 18 Nov 2022 05:32:06 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Kevin Tian , Will Deacon , Robin Murphy , Liu Yi L , Jacob jun Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v4 1/7] iommu/vt-d: Allocate pasid table in device probe path Date: Fri, 18 Nov 2022 21:24:45 +0800 Message-Id: <20221118132451.114406-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118132451.114406-1-baolu.lu@linux.intel.com> References: <20221118132451.114406-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Whether or not a domain is attached to the device, the pasid table should always be valid as long as it has been probed. This moves the pasid table allocation from the domain attaching device path to device probe path and frees it in the device release path. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 996a8b5ee5ee..6b8a24f68da8 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2475,13 +2475,6 @@ static int domain_add_dev_info(struct dmar_domain *d= omain, struct device *dev) =20 /* PASID table is mandatory for a PCI device in scalable mode. */ if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) { - ret =3D intel_pasid_alloc_table(dev); - if (ret) { - dev_err(dev, "PASID table allocation failed\n"); - dmar_remove_one_dev_info(dev); - return ret; - } - /* Setup the PASID entry for requests without PASID: */ if (hw_pass_through && domain_type_is_si(domain)) ret =3D intel_pasid_setup_pass_through(iommu, domain, @@ -4106,7 +4099,6 @@ static void dmar_remove_one_dev_info(struct device *d= ev) =20 iommu_disable_dev_iotlb(info); domain_context_clear(info); - intel_pasid_free_table(info->dev); } =20 spin_lock_irqsave(&domain->lock, flags); @@ -4466,6 +4458,7 @@ static struct iommu_device *intel_iommu_probe_device(= struct device *dev) struct device_domain_info *info; struct intel_iommu *iommu; u8 bus, devfn; + int ret; =20 iommu =3D device_to_iommu(dev, &bus, &devfn); if (!iommu || !iommu->iommu.ops) @@ -4509,6 +4502,16 @@ static struct iommu_device *intel_iommu_probe_device= (struct device *dev) =20 dev_iommu_priv_set(dev, info); =20 + if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) { + ret =3D intel_pasid_alloc_table(dev); + if (ret) { + dev_err(dev, "PASID table allocation failed\n"); + dev_iommu_priv_set(dev, NULL); + kfree(info); + return ERR_PTR(ret); + } + } + return &iommu->iommu; } =20 @@ -4517,6 +4520,7 @@ static void intel_iommu_release_device(struct device = *dev) struct device_domain_info *info =3D dev_iommu_priv_get(dev); =20 dmar_remove_one_dev_info(dev); + intel_pasid_free_table(dev); dev_iommu_priv_set(dev, NULL); kfree(info); set_dma_ops(dev, NULL); --=20 2.34.1 From nobody Fri Dec 19 20:15:53 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6AFDC433FE for ; Fri, 18 Nov 2022 13:32:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242152AbiKRNc4 (ORCPT ); Fri, 18 Nov 2022 08:32:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242097AbiKRNcR (ORCPT ); Fri, 18 Nov 2022 08:32:17 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51DFC7FC23 for ; Fri, 18 Nov 2022 05:32:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668778336; x=1700314336; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RfcpiEbdbskkPeCw2JzA4bI6d0W2gVvyufESQpbn4Bk=; b=bBHZu+ppST+XqpJhGOQLTqREmdEzh9Zj/k/iumYAJLTOnIsejkZy0QTN lzQC9HuMwbSg8Fi87chlt3enqH2s6jMlH2JJ/RSyXz4znKvNcnmF644KK jH+OOzQkYRGn0UsYjliFzEzeMaLOvuWvp1uQfjFR8S6Hc9LlEhLWnVMFK hbRszyOU7NFww1tTi7OeuzCf0pGb5n2rge9m0hojELQP3Rpn5tI18Tjdo 5fnujuBM2oO0Z9YnWk0ntdcgFlCi65kWmRxX2lwFzA6EnCz7AZwWKoRKK GXNtBZ7TSr0rIgKDLaGIDOcnczqAWSAzd8Dh9X8l1+LI+qL0twAYiklxV g==; X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="314285094" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="314285094" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 05:32:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="642512007" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="642512007" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga007.fm.intel.com with ESMTP; 18 Nov 2022 05:32:09 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Kevin Tian , Will Deacon , Robin Murphy , Liu Yi L , Jacob jun Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v4 2/7] iommu/vt-d: Add device_block_translation() helper Date: Fri, 18 Nov 2022 21:24:46 +0800 Message-Id: <20221118132451.114406-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118132451.114406-1-baolu.lu@linux.intel.com> References: <20221118132451.114406-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If domain attaching to device fails, the IOMMU driver should bring the device to blocking DMA state. The upper layer is expected to recover it by attaching a new domain. Use device_block_translation() in the error path of dev_attach to make the behavior specific. The difference between device_block_translation() and the previous dmar_remove_one_dev_info() is that, in the scalable mode, it is the RID2PASID entry instead of context entry being cleared. As a result, enabling PCI capabilities is moved up. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 44 ++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 6b8a24f68da8..6aafb86ef5c3 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -277,7 +277,7 @@ static LIST_HEAD(dmar_satc_units); #define for_each_rmrr_units(rmrr) \ list_for_each_entry(rmrr, &dmar_rmrr_units, list) =20 -static void dmar_remove_one_dev_info(struct device *dev); +static void device_block_translation(struct device *dev); =20 int dmar_disabled =3D !IS_ENABLED(CONFIG_INTEL_IOMMU_DEFAULT_ON); int intel_iommu_sm =3D IS_ENABLED(CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT= _ON); @@ -1400,7 +1400,7 @@ static void iommu_enable_pci_caps(struct device_domai= n_info *info) { struct pci_dev *pdev; =20 - if (!info || !dev_is_pci(info->dev)) + if (!dev_is_pci(info->dev)) return; =20 pdev =3D to_pci_dev(info->dev); @@ -2045,7 +2045,6 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, } else { iommu_flush_write_buffer(iommu); } - iommu_enable_pci_caps(info); =20 ret =3D 0; =20 @@ -2487,7 +2486,7 @@ static int domain_add_dev_info(struct dmar_domain *do= main, struct device *dev) dev, PASID_RID2PASID); if (ret) { dev_err(dev, "Setup RID2PASID failed\n"); - dmar_remove_one_dev_info(dev); + device_block_translation(dev); return ret; } } @@ -2495,10 +2494,12 @@ static int domain_add_dev_info(struct dmar_domain *= domain, struct device *dev) ret =3D domain_context_mapping(domain, dev); if (ret) { dev_err(dev, "Domain context map failed\n"); - dmar_remove_one_dev_info(dev); + device_block_translation(dev); return ret; } =20 + iommu_enable_pci_caps(info); + return 0; } =20 @@ -4109,6 +4110,37 @@ static void dmar_remove_one_dev_info(struct device *= dev) info->domain =3D NULL; } =20 +/* + * Clear the page table pointer in context or pasid table entries so that + * all DMA requests without PASID from the device are blocked. If the page + * table has been set, clean up the data structures. + */ +static void device_block_translation(struct device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + unsigned long flags; + + iommu_disable_dev_iotlb(info); + if (!dev_is_real_dma_subdevice(dev)) { + if (sm_supported(iommu)) + intel_pasid_tear_down_entry(iommu, dev, + PASID_RID2PASID, false); + else + domain_context_clear(info); + } + + if (!info->domain) + return; + + spin_lock_irqsave(&info->domain->lock, flags); + list_del(&info->link); + spin_unlock_irqrestore(&info->domain->lock, flags); + + domain_detach_iommu(info->domain, iommu); + info->domain =3D NULL; +} + static int md_domain_init(struct dmar_domain *domain, int guest_width) { int adjust_width; @@ -4232,7 +4264,7 @@ static int intel_iommu_attach_device(struct iommu_dom= ain *domain, struct device_domain_info *info =3D dev_iommu_priv_get(dev); =20 if (info->domain) - dmar_remove_one_dev_info(dev); + device_block_translation(dev); } =20 ret =3D prepare_domain_attach_device(domain, dev); --=20 2.34.1 From nobody Fri Dec 19 20:15:53 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5887CC4332F for ; Fri, 18 Nov 2022 13:33:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242158AbiKRNc6 (ORCPT ); Fri, 18 Nov 2022 08:32:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242098AbiKRNcR (ORCPT ); Fri, 18 Nov 2022 08:32:17 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 136AB725C0 for ; Fri, 18 Nov 2022 05:32:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668778337; x=1700314337; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8S80uWfDgSB0BEFNRpbkXlNBuJDV0mgSaia/IS252F8=; b=I3uRHK2sDuAhFwvFrpYfVywNDh9QmoKuLvUy/FZnNt4Og7VD7wtLfK81 05wv+rBcptZ1v2Q0hKMuRTyLSqS5NKefBCQwzmH1DgkFwDaxMyaBD0I68 sAxajvWFbzwIVqlz6pnNrKT/pKFzFziEp4g5REyDCS8WbzRWHStMFg82c lCmNrtppuXTzbS0NLbCmEgJuYYrITlVrT6Y78xzjSTzs15ohnLzNDT1q/ BWK12x+55p+rgYesAqLlOdk0VptfOZr6MwTV1flo001oh50OOZMaD2tXb E4dkMvYC3Pk8LZrPLsHa6u81x4O2kPBu6Z8WArgB15Caj/MHWNBVkToUZ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="314285099" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="314285099" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 05:32:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="642512020" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="642512020" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga007.fm.intel.com with ESMTP; 18 Nov 2022 05:32:11 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Kevin Tian , Will Deacon , Robin Murphy , Liu Yi L , Jacob jun Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v4 3/7] iommu/vt-d: Add blocking domain support Date: Fri, 18 Nov 2022 21:24:47 +0800 Message-Id: <20221118132451.114406-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118132451.114406-1-baolu.lu@linux.intel.com> References: <20221118132451.114406-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Intel IOMMU hardwares support blocking DMA transactions by clearing the translation table entries. This implements a real blocking domain to avoid using an empty UNMANAGED domain. The detach_dev callback of the domain ops is not used in any path. Remove it to avoid dead code as well. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 6aafb86ef5c3..25c772e8106f 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -278,6 +278,7 @@ static LIST_HEAD(dmar_satc_units); list_for_each_entry(rmrr, &dmar_rmrr_units, list) =20 static void device_block_translation(struct device *dev); +static void intel_iommu_domain_free(struct iommu_domain *domain); =20 int dmar_disabled =3D !IS_ENABLED(CONFIG_INTEL_IOMMU_DEFAULT_ON); int intel_iommu_sm =3D IS_ENABLED(CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT= _ON); @@ -4162,12 +4163,28 @@ static int md_domain_init(struct dmar_domain *domai= n, int guest_width) return 0; } =20 +static int blocking_domain_attach_dev(struct iommu_domain *domain, + struct device *dev) +{ + device_block_translation(dev); + return 0; +} + +static struct iommu_domain blocking_domain =3D { + .ops =3D &(const struct iommu_domain_ops) { + .attach_dev =3D blocking_domain_attach_dev, + .free =3D intel_iommu_domain_free + } +}; + static struct iommu_domain *intel_iommu_domain_alloc(unsigned type) { struct dmar_domain *dmar_domain; struct iommu_domain *domain; =20 switch (type) { + case IOMMU_DOMAIN_BLOCKED: + return &blocking_domain; case IOMMU_DOMAIN_DMA: case IOMMU_DOMAIN_DMA_FQ: case IOMMU_DOMAIN_UNMANAGED: @@ -4200,7 +4217,7 @@ static struct iommu_domain *intel_iommu_domain_alloc(= unsigned type) =20 static void intel_iommu_domain_free(struct iommu_domain *domain) { - if (domain !=3D &si_domain->domain) + if (domain !=3D &si_domain->domain && domain !=3D &blocking_domain) domain_exit(to_dmar_domain(domain)); } =20 @@ -4274,12 +4291,6 @@ static int intel_iommu_attach_device(struct iommu_do= main *domain, return domain_add_dev_info(to_dmar_domain(domain), dev); } =20 -static void intel_iommu_detach_device(struct iommu_domain *domain, - struct device *dev) -{ - dmar_remove_one_dev_info(dev); -} - static int intel_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t hpa, size_t size, int iommu_prot, gfp_t gfp) @@ -4767,7 +4778,6 @@ const struct iommu_ops intel_iommu_ops =3D { #endif .default_domain_ops =3D &(const struct iommu_domain_ops) { .attach_dev =3D intel_iommu_attach_device, - .detach_dev =3D intel_iommu_detach_device, .map_pages =3D intel_iommu_map_pages, .unmap_pages =3D intel_iommu_unmap_pages, .iotlb_sync_map =3D intel_iommu_iotlb_sync_map, --=20 2.34.1 From nobody Fri Dec 19 20:15:53 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48F02C433FE for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="314285104" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="314285104" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 05:32:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="642512033" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="642512033" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga007.fm.intel.com with ESMTP; 18 Nov 2022 05:32:13 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Kevin Tian , Will Deacon , Robin Murphy , Liu Yi L , Jacob jun Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v4 4/7] iommu/vt-d: Rename iommu_disable_dev_iotlb() Date: Fri, 18 Nov 2022 21:24:48 +0800 Message-Id: <20221118132451.114406-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118132451.114406-1-baolu.lu@linux.intel.com> References: <20221118132451.114406-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rename iommu_disable_dev_iotlb() to iommu_disable_pci_caps() to pair with iommu_enable_pci_caps(). Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 25c772e8106f..a5885665ccef 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1441,7 +1441,7 @@ static void iommu_enable_pci_caps(struct device_domai= n_info *info) } } =20 -static void iommu_disable_dev_iotlb(struct device_domain_info *info) +static void iommu_disable_pci_caps(struct device_domain_info *info) { struct pci_dev *pdev; =20 @@ -4099,7 +4099,7 @@ static void dmar_remove_one_dev_info(struct device *d= ev) intel_pasid_tear_down_entry(iommu, info->dev, PASID_RID2PASID, false); =20 - iommu_disable_dev_iotlb(info); + iommu_disable_pci_caps(info); domain_context_clear(info); } =20 @@ -4122,7 +4122,7 @@ static void device_block_translation(struct device *d= ev) struct intel_iommu *iommu =3D info->iommu; unsigned long flags; =20 - iommu_disable_dev_iotlb(info); + iommu_disable_pci_caps(info); if (!dev_is_real_dma_subdevice(dev)) { if (sm_supported(iommu)) intel_pasid_tear_down_entry(iommu, dev, --=20 2.34.1 From nobody Fri Dec 19 20:15:53 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BC45C4332F for ; Fri, 18 Nov 2022 13:33:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242168AbiKRNdF (ORCPT ); Fri, 18 Nov 2022 08:33:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242113AbiKRNcT (ORCPT ); Fri, 18 Nov 2022 08:32:19 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 228598D4BD for ; Fri, 18 Nov 2022 05:32:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668778339; x=1700314339; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZFINOeY0qWVoM/bkOJT0DrDVTz+kLKxbWYnAUaePQp0=; b=YbeDF8wWJAoxb4l5RlNWUVArP+v72m8+L0dsMPTdJTbacdRV0XLmsnjC kN5O4lE5eZtHdFZYXmPR6BjYP0wi6rUtjJW8zzquGJWzb2Mi/r8BHq94X M5MfC0ee7etUCNZYaG1WjNAqBAhBittJDKwERX4FsgX4r2egFJzGKbEqC VlCi7IyAINzpNVUGpQ8x3Xqs/akj8o3tNuz3fGBuatudGEsSX8T+0yaRQ G8VILKnbpOQ7zx8nmgfSI/7V2BK9E7S4GIm0AFr2GVMAMUgLmnCKtrKis yLQhOnf8dC+LWM40t+OUXPSU1OhuAyDCzB6ChEnutlrlFWLP5TiROwgJr w==; X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="314285110" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="314285110" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 05:32:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="642512043" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="642512043" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga007.fm.intel.com with ESMTP; 18 Nov 2022 05:32:16 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Kevin Tian , Will Deacon , Robin Murphy , Liu Yi L , Jacob jun Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v4 5/7] iommu/vt-d: Rename domain_add_dev_info() Date: Fri, 18 Nov 2022 21:24:49 +0800 Message-Id: <20221118132451.114406-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118132451.114406-1-baolu.lu@linux.intel.com> References: <20221118132451.114406-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" dmar_domain_attach_device() is more meaningful according to what this helper does. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index a5885665ccef..3bd79ae238f2 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2453,7 +2453,8 @@ static int __init si_domain_init(int hw) return 0; } =20 -static int domain_add_dev_info(struct dmar_domain *domain, struct device *= dev) +static int dmar_domain_attach_device(struct dmar_domain *domain, + struct device *dev) { struct device_domain_info *info =3D dev_iommu_priv_get(dev); struct intel_iommu *iommu; @@ -4288,7 +4289,7 @@ static int intel_iommu_attach_device(struct iommu_dom= ain *domain, if (ret) return ret; =20 - return domain_add_dev_info(to_dmar_domain(domain), dev); + return dmar_domain_attach_device(to_dmar_domain(domain), dev); } =20 static int intel_iommu_map(struct iommu_domain *domain, --=20 2.34.1 From nobody Fri Dec 19 20:15:53 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75B0AC433FE for ; Fri, 18 Nov 2022 13:33:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242059AbiKRNdK (ORCPT ); Fri, 18 Nov 2022 08:33:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241422AbiKRNcW (ORCPT ); Fri, 18 Nov 2022 08:32:22 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88117FC for ; Fri, 18 Nov 2022 05:32:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668778341; x=1700314341; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yUafzpnLyJgsHBRq17y9522W4lhffFNC0HRDUpuX5cs=; b=HIt/Q779uIgJ6jWpOf6WTwUzVEtwv4zDNhnI0VqApTZH9rOZH7mTsknW 7SNUxKf8DC14uxW95acCJKQaxvKNI8crcqjVuUCFLxec4GfMJTu9FoqqK klZq5wZjOaY9p4HTOcxEW3svjDVqzPjRvhqL9flQXXLOQVNOefD/+Z1Y4 BJ7Chl+XSHCvY+s4y/6hj/VAkmGQDUkZfK/TpdbSP435cJgjbEBcVsH/k 4Lxz64St4/4yrGrBSo8/o1Jd/CM7YHEIcswinqDz8OnFnuCXEQ/XiX3cx sRG+nYCW3ZPtRVbOnxizB6eAzInuPHA3mto/XDy5Ynm7zkuEqAf0zxBbY A==; X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="314285119" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="314285119" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 05:32:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="642512050" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="642512050" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga007.fm.intel.com with ESMTP; 18 Nov 2022 05:32:19 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Kevin Tian , Will Deacon , Robin Murphy , Liu Yi L , Jacob jun Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v4 6/7] iommu/vt-d: Remove unnecessary domain_context_mapped() Date: Fri, 18 Nov 2022 21:24:50 +0800 Message-Id: <20221118132451.114406-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118132451.114406-1-baolu.lu@linux.intel.com> References: <20221118132451.114406-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The device_domain_info::domain accurately records the domain attached to the device. It is unnecessary to check whether the context is present in the attach_dev path. Remove it to make the code neat. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 47 +++---------------------------------- 1 file changed, 3 insertions(+), 44 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 3bd79ae238f2..3b37f1b3b6de 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -780,19 +780,6 @@ static void domain_flush_cache(struct dmar_domain *dom= ain, clflush_cache_range(addr, size); } =20 -static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 dev= fn) -{ - struct context_entry *context; - int ret =3D 0; - - spin_lock(&iommu->lock); - context =3D iommu_context_addr(iommu, bus, devfn, 0); - if (context) - ret =3D context_present(context); - spin_unlock(&iommu->lock); - return ret; -} - static void free_context_table(struct intel_iommu *iommu) { struct context_entry *context; @@ -2097,30 +2084,6 @@ domain_context_mapping(struct dmar_domain *domain, s= truct device *dev) &domain_context_mapping_cb, &data); } =20 -static int domain_context_mapped_cb(struct pci_dev *pdev, - u16 alias, void *opaque) -{ - struct intel_iommu *iommu =3D opaque; - - return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff); -} - -static int domain_context_mapped(struct device *dev) -{ - struct intel_iommu *iommu; - u8 bus, devfn; - - iommu =3D device_to_iommu(dev, &bus, &devfn); - if (!iommu) - return -ENODEV; - - if (!dev_is_pci(dev)) - return device_context_mapped(iommu, bus, devfn); - - return !pci_for_each_dma_alias(to_pci_dev(dev), - domain_context_mapped_cb, iommu); -} - /* Returns a number of VTD pages, but aligned to MM page size */ static inline unsigned long aligned_nrpages(unsigned long host_addr, size_t size) @@ -4269,6 +4232,7 @@ static int prepare_domain_attach_device(struct iommu_= domain *domain, static int intel_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { + struct device_domain_info *info =3D dev_iommu_priv_get(dev); int ret; =20 if (domain->type =3D=3D IOMMU_DOMAIN_UNMANAGED && @@ -4277,13 +4241,8 @@ static int intel_iommu_attach_device(struct iommu_do= main *domain, return -EPERM; } =20 - /* normally dev is not mapped */ - if (unlikely(domain_context_mapped(dev))) { - struct device_domain_info *info =3D dev_iommu_priv_get(dev); - - if (info->domain) - device_block_translation(dev); - } + if (info->domain) + device_block_translation(dev); =20 ret =3D prepare_domain_attach_device(domain, dev); if (ret) --=20 2.34.1 From nobody Fri Dec 19 20:15:53 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AB62C433FE for ; Fri, 18 Nov 2022 13:33:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241810AbiKRNdS (ORCPT ); Fri, 18 Nov 2022 08:33:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242111AbiKRNcY (ORCPT ); Fri, 18 Nov 2022 08:32:24 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDBFC13F4D for ; Fri, 18 Nov 2022 05:32:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668778343; x=1700314343; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xvQUqZl0oZLTlkNsZV1wcJYvypgnpkuAf9YqsYahmxw=; b=heSpqMZ92bDX4Kcxc4U74V3FdV7dgkNlQMAV/HDKE4QuIhKADUAVXcEs 0/2Wi4rlCjF+BNTajJg97kbu+KJRMW9lTpqIVE9eHrB3P5rx/+eP/a/+l zMd45ZPoUE/ZobEdYPLzvELC2U2FRjxpBGw88mEouMPhzRnKubt/8TNHp tKFzCfAJwDzHbUONVnoFIb/aBlinilr9RM6pjH0DeZTr1hXzhlgnkv289 0NL3i400XNIA9d/fFZDg1iYq3hWrQAdXC6xR6W2bnPYHOrLVypCdQwSmQ p4ge0faq7zbsYy3MARAtnzVewMtHOKAKMGmVbHd0zNB+Ataayn00TgdVV w==; X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="314285124" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="314285124" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 05:32:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="642512056" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="642512056" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga007.fm.intel.com with ESMTP; 18 Nov 2022 05:32:21 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Kevin Tian , Will Deacon , Robin Murphy , Liu Yi L , Jacob jun Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v4 7/7] iommu/vt-d: Use real field for indication of first level Date: Fri, 18 Nov 2022 21:24:51 +0800 Message-Id: <20221118132451.114406-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118132451.114406-1-baolu.lu@linux.intel.com> References: <20221118132451.114406-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The dmar_domain uses bit field members to indicate the behaviors. Add a bit field for using first level and remove the flags member to avoid duplication. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.h | 15 +++++---------- drivers/iommu/intel/iommu.c | 25 ++++++++++--------------- 2 files changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 92023dff9513..30b0d72aeb6c 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -517,14 +517,6 @@ struct context_entry { u64 hi; }; =20 -/* - * When VT-d works in the scalable mode, it allows DMA translation to - * happen through either first level or second level page table. This - * bit marks that the DMA translation for the domain goes through the - * first level page table, otherwise, it goes through the second level. - */ -#define DOMAIN_FLAG_USE_FIRST_LEVEL BIT(1) - struct iommu_domain_info { struct intel_iommu *iommu; unsigned int refcnt; /* Refcount of devices per iommu */ @@ -541,6 +533,11 @@ struct dmar_domain { u8 iommu_coherency: 1; /* indicate coherency of iommu access */ u8 force_snooping : 1; /* Create IOPTEs with snoop control */ u8 set_pte_snp:1; + u8 use_first_level:1; /* DMA translation for the domain goes + * through the first level page table, + * otherwise, goes through the second + * level. + */ =20 spinlock_t lock; /* Protect device tracking lists */ struct list_head devices; /* all devices' list */ @@ -550,8 +547,6 @@ struct dmar_domain { =20 /* adjusted guest address width, 0 is level 2 30-bit */ int agaw; - - int flags; /* flags to find out type of domain */ int iommu_superpage;/* Level of superpages supported: 0 =3D=3D 4KiB (no superpages), 1 =3D=3D 2MiB, 2 =3D=3D 1GiB, 3 =3D=3D 512GiB, 4 =3D=3D 1TiB */ diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 3b37f1b3b6de..a3db7ac3d60c 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -383,11 +383,6 @@ static inline int domain_type_is_si(struct dmar_domain= *domain) return domain->domain.type =3D=3D IOMMU_DOMAIN_IDENTITY; } =20 -static inline bool domain_use_first_level(struct dmar_domain *domain) -{ - return domain->flags & DOMAIN_FLAG_USE_FIRST_LEVEL; -} - static inline int domain_pfn_supported(struct dmar_domain *domain, unsigned long pfn) { @@ -501,7 +496,7 @@ static int domain_update_iommu_superpage(struct dmar_do= main *domain, rcu_read_lock(); for_each_active_iommu(iommu, drhd) { if (iommu !=3D skip) { - if (domain && domain_use_first_level(domain)) { + if (domain && domain->use_first_level) { if (!cap_fl1gp_support(iommu->cap)) mask =3D 0x1; } else { @@ -579,7 +574,7 @@ static void domain_update_iommu_cap(struct dmar_domain = *domain) * paging and 57-bits with 5-level paging). Hence, skip bit * [N-1]. */ - if (domain_use_first_level(domain)) + if (domain->use_first_level) domain->domain.geometry.aperture_end =3D __DOMAIN_MAX_ADDR(domain->gaw -= 1); else domain->domain.geometry.aperture_end =3D __DOMAIN_MAX_ADDR(domain->gaw); @@ -947,7 +942,7 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domai= n *domain, =20 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); pteval =3D ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DM= A_PTE_READ | DMA_PTE_WRITE; - if (domain_use_first_level(domain)) + if (domain->use_first_level) pteval |=3D DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; =20 if (cmpxchg64(&pte->val, 0ULL, pteval)) @@ -1498,7 +1493,7 @@ static void iommu_flush_iotlb_psi(struct intel_iommu = *iommu, if (ih) ih =3D 1 << 6; =20 - if (domain_use_first_level(domain)) { + if (domain->use_first_level) { qi_flush_piotlb(iommu, did, PASID_RID2PASID, addr, pages, ih); } else { unsigned long bitmask =3D aligned_pages - 1; @@ -1552,7 +1547,7 @@ static inline void __mapping_notify_one(struct intel_= iommu *iommu, * It's a non-present to present mapping. Only flush if caching mode * and second level. */ - if (cap_caching_mode(iommu->cap) && !domain_use_first_level(domain)) + if (cap_caching_mode(iommu->cap) && !domain->use_first_level) iommu_flush_iotlb_psi(iommu, domain, pfn, pages, 0, 1); else iommu_flush_write_buffer(iommu); @@ -1568,7 +1563,7 @@ static void intel_flush_iotlb_all(struct iommu_domain= *domain) struct intel_iommu *iommu =3D info->iommu; u16 did =3D domain_id_iommu(dmar_domain, iommu); =20 - if (domain_use_first_level(dmar_domain)) + if (dmar_domain->use_first_level) qi_flush_piotlb(iommu, did, PASID_RID2PASID, 0, -1, 0); else iommu->flush.flush_iotlb(iommu, did, 0, 0, @@ -1741,7 +1736,7 @@ static struct dmar_domain *alloc_domain(unsigned int = type) =20 domain->nid =3D NUMA_NO_NODE; if (first_level_by_default(type)) - domain->flags |=3D DOMAIN_FLAG_USE_FIRST_LEVEL; + domain->use_first_level =3D true; domain->has_iotlb_device =3D false; INIT_LIST_HEAD(&domain->devices); spin_lock_init(&domain->lock); @@ -2173,7 +2168,7 @@ __domain_mapping(struct dmar_domain *domain, unsigned= long iov_pfn, =20 attr =3D prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP); attr |=3D DMA_FL_PTE_PRESENT; - if (domain_use_first_level(domain)) { + if (domain->use_first_level) { attr |=3D DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; if (prot & DMA_PTE_WRITE) attr |=3D DMA_FL_PTE_DIRTY; @@ -2443,7 +2438,7 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, if (hw_pass_through && domain_type_is_si(domain)) ret =3D intel_pasid_setup_pass_through(iommu, domain, dev, PASID_RID2PASID); - else if (domain_use_first_level(domain)) + else if (domain->use_first_level) ret =3D domain_setup_first_level(iommu, domain, dev, PASID_RID2PASID); else @@ -4412,7 +4407,7 @@ static void domain_set_force_snooping(struct dmar_dom= ain *domain) * Second level page table supports per-PTE snoop control. The * iommu_map() interface will handle this by setting SNP bit. */ - if (!domain_use_first_level(domain)) { + if (!domain->use_first_level) { domain->set_pte_snp =3D true; return; } --=20 2.34.1