From nobody Sat Sep 21 12:47:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77D1EC433FE for ; Fri, 18 Nov 2022 11:32:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241098AbiKRLco (ORCPT ); Fri, 18 Nov 2022 06:32:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241062AbiKRLcN (ORCPT ); Fri, 18 Nov 2022 06:32:13 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA39C7CBB0; Fri, 18 Nov 2022 03:31:59 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id l39-20020a05600c1d2700b003cf93c8156dso3811309wms.4; Fri, 18 Nov 2022 03:31:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=32Tw0VIB3bjFmOplr9SeFowbh/PeKCbbj6BvYAFnrkk=; b=FuavVFY2KSnenYdp+tweCYsgI4Oogrs8UL/LxHNEuXc7/P8xIZDxr5nrAdjyR7pMB5 ZJiqAetUiPLcXGvkMLmizQd0bT5i5+GADcBmWEISrtRPDY5Ty86seVhRD7+fZR/z5t2S CWEe6PHN0wx8/VRSlOyn8h8M0is/l1MP1de0UflJzo3+mSrx6v+fmrZ+mYPmWI2ewMpB 4wFKuSNTca7NFwAEINzyfzOMq8lF6Kst1AK6jy36FR8W6F81S9cfh7SDsrLk8sHVfp5+ K848FbnjzGed972D7OjS70PTBg9oycxk8vbKkVLFRHtF+WejTf9M92ODVtk7pM5fpPwk 2mZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=32Tw0VIB3bjFmOplr9SeFowbh/PeKCbbj6BvYAFnrkk=; b=dMH2mhvBp3jSiCVCTYgEe4A2rvuI6/I2Q0kYLhCPKkgjuqU+OaIGAPJR4mUwZi7m8T 9AlcJDQkcarokYcDqJY13tm+joJhbMe1FJLlLEer4vDD3MptMC9SrR+720FMr/EHI2cs 3vPtpq/bCmo3VJAH45WXC/4FJCWrn7wWp+wCsK7hGocJPiL93k5HUWLrY32M1otQjsN1 7ezUsFltCADAUivU/IpLum/zftOWZ1xpLQtCc9FitQTvCDEtKqBqGxXzyqZu+i2y2v16 2vaeSixQUb1IWPCJaChMwhQmBjMqdBdf2Fez8ZyDa2OF7zTwFvF37MAhy4isU9v3i2aW N4ug== X-Gm-Message-State: ANoB5pmbTq0IfEJgOZVt19JI0fuB0EBooVRYETPDJlGH4ZoArTNsdDDg a9iBazErzbJ6Bk/fO+f2n+bEy1teu6k= X-Google-Smtp-Source: AA0mqf7NW9yZKRf3UJ98dIUGoFgOP0RBPYcC7dkMwUvCCKlP3Fg72FEyuExdEOvXuo9RFoCGsonH9w== X-Received: by 2002:a1c:f216:0:b0:3c6:c2ae:278b with SMTP id s22-20020a1cf216000000b003c6c2ae278bmr4547325wmc.127.1668771118235; Fri, 18 Nov 2022 03:31:58 -0800 (PST) Received: from localhost.localdomain ([95.183.227.98]) by smtp.gmail.com with ESMTPSA id l24-20020a05600c1d1800b003cf878c4468sm9894817wms.5.2022.11.18.03.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 03:31:57 -0800 (PST) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Andy Teng , AngeloGioacchino Del Regno Cc: Yassine Oudjana , Yassine Oudjana , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/7] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Pull pinctrl node changes from MT6795 document Date: Fri, 18 Nov 2022 14:30:22 +0300 Message-Id: <20221118113028.145348-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221118113028.145348-1-y.oudjana@protonmail.com> References: <20221118113028.145348-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana mediatek,pinctrl-mt6795.yaml has different node name patterns which match bindings of other MediaTek pin controllers, ref for pinmux-node.yaml which has a description of the pinmux property, as well as some additional descriptions for some pin configuration properties. Pull those changes into mediatek,mt6779-pinctrl.yaml and adjust the example DTS to match in preparation to combine the MT6795 document into it. Signed-off-by: Yassine Oudjana --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 38 ++++++++++++++----- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctr= l.yaml index a2141eb0854e..d6231d11e949 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -111,19 +111,21 @@ allOf: - "#interrupt-cells" =20 patternProperties: - '-[0-9]*$': + '-pins$': type: object additionalProperties: false =20 patternProperties: - '-pins*$': + '^pins': type: object description: | A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer configuration, pullups, drive strength, input enable/disable and= input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + allOf: + - $ref: pinmux-node.yaml + - $ref: pincfg-node.yaml =20 properties: pinmux: @@ -134,9 +136,25 @@ patternProperties: =20 bias-disable: true =20 - bias-pull-up: true - - bias-pull-down: true + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull up PUPD/R0/R1 type define value. + description: | + For normal pull up type, it is not necessary to specify R1R0 + values; When pull up type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull down PUPD/R0/R1 type define value. + description: | + For normal pull down type, it is not necessary to specify R1= R0 + values; When pull down type is PUPD/R0/R1, adding R1R0 defin= es + will set different resistance values. =20 input-enable: true =20 @@ -218,8 +236,8 @@ examples: #interrupt-cells =3D <2>; interrupts =3D ; =20 - mmc0_pins_default: mmc0-0 { - cmd-dat-pins { + mmc0_pins_default: mmc0-pins { + pins-cmd-dat { pinmux =3D , , , @@ -232,11 +250,11 @@ examples: input-enable; mediatek,pull-up-adv =3D <1>; }; - clk-pins { + pins-clk { pinmux =3D ; mediatek,pull-down-adv =3D <2>; }; - rst-pins { + pins-rst { pinmux =3D ; mediatek,pull-up-adv =3D <0>; }; --=20 2.38.1