From nobody Sat Sep 21 09:47:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7ED2C43217 for ; Thu, 17 Nov 2022 21:05:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240711AbiKQVFK (ORCPT ); Thu, 17 Nov 2022 16:05:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240226AbiKQVEu (ORCPT ); Thu, 17 Nov 2022 16:04:50 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49AF882232 for ; Thu, 17 Nov 2022 13:04:06 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id i10so8227564ejg.6 for ; Thu, 17 Nov 2022 13:04:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kAZa5MFL/kgwwXWrMqu8oN1aUslhiGgDdUjW81Mvb9E=; b=XZBw/6JKc5rCyqd38GXo449XIEv3Pgnx/zV+EwB6bkMu7QdA3f5UMa5tHMvBjgZzBE uEKwrFE3SAZzIrnNf8MlwfrdlexUb7BK9KXsHO4ejyvxWkBQVNQ2OJPE5TGb6kKFePGW 52Rll9OU9NXj61EHN95qVgdUAGOGZoNuhhtZJCVgbrSsiBtj4XK2RVNkmi8IAFBcnU1j 9q98v1XEcO+CtNDuXUYYbW0usND2Y5IEcutXWvldYBMTxQvk6+U8/S9fQsfAiAWKYVCG hrba6pp1uZjPT4F7OIuywMumhy6TP2IAQNMwSiI/0uBADkwix95zhfEFzcQXdRYPmfkl OCLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kAZa5MFL/kgwwXWrMqu8oN1aUslhiGgDdUjW81Mvb9E=; b=igrk+TXoVf2iVJtgkONIWBTCbH1e1jSF5fZdsV7zWP1KYqRHGF8zxBDIxGueLaDmOW 27mAT28tv2Qwf3/JQMC59WEzqOx1MfXiJJ7f5QOWjD/1gST38nqUyZheaT00A/oZm4EX P1rNqhlZjLiivm16myznZGA61LNFThLBo/mmcVi1aqY13UkD2aJxk5zb5Km6LCr2xDse EjBiI8KQDkE0EPc4DORBPEzWb4VSeD2hiWLZis4no6eZRz3jnZEc8Shtkr/2DDwVamJS rHCRcTQLicHeYrkMtgMaOdGQPOdK2VlSicWx5Zh9ftU9Ezl5BaZifOtBxp+nHo+/yWQB Wgkg== X-Gm-Message-State: ANoB5pl8uv3lgxQwHSl/NSIuMb5luH96t+uBGV77uG013CN0CAdjgSmL Ijs8uHNTf9/QJvZiInao7ucloA== X-Google-Smtp-Source: AA0mqf6W3sFv9vFKd6YCkQLpyKtG+CyoNEaecRwrtqA8rwwNVI7AEZQPgXiyZgWKtmNic/zKOZsXeg== X-Received: by 2002:a17:906:3385:b0:7a2:b352:a0d3 with SMTP id v5-20020a170906338500b007a2b352a0d3mr3502702eja.399.1668719044782; Thu, 17 Nov 2022 13:04:04 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:04 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 1/7] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board Date: Thu, 17 Nov 2022 22:03:50 +0100 Message-Id: <20221117210356.3178578-2-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for the Mediatek mt8365-evk board. Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 7642f9350d2c0..a9c18fc7905c0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -243,6 +243,10 @@ properties: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8365-evk + - const: mediatek, mt8365 - items: - enum: - mediatek,mt8516-pumpkin --=20 2.38.1 From nobody Sat Sep 21 09:47:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC667C433FE for ; Thu, 17 Nov 2022 21:05:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240633AbiKQVFN (ORCPT ); Thu, 17 Nov 2022 16:05:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240705AbiKQVEv (ORCPT ); Thu, 17 Nov 2022 16:04:51 -0500 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B18D48E2AE for ; Thu, 17 Nov 2022 13:04:07 -0800 (PST) Received: by mail-ej1-x62c.google.com with SMTP id ud5so8250595ejc.4 for ; Thu, 17 Nov 2022 13:04:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X3nU7X0djX9jQ80iI8+t0kZ5Fy4kB3s5F+snjwXKwEE=; b=x0/2+JLtr5Wevfc3DaNs8djNaF+ABrzMQdBLyBvmMIRdvFr6TTAal/W4ymfMF/LlMm UmJRTSm/5ZTxaaFM+jIxzkNZt/gGSeS94TkXx6WN8rWl7SsHcL0P9Dzz+sVnmPvFa5OY zJe1wFSiHOnYcbK5spt/YUA+pX2CpMN2X5HCQxWMCok+28apKKiMYIznTp6dENuNVIbH 5a4KZsa0LSxYYLUSkVZ5hMRsVQ4tnnjBL2eq0rB9hADwj/LotVke1a/rmuiScWKgwFPb 9yHqrhNxV5adPmAm5q/DnxiqoWKxH/nf/e9WDHuxJHHT6hh3r0fpL+BaiJqrcrxrqF5D oPBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X3nU7X0djX9jQ80iI8+t0kZ5Fy4kB3s5F+snjwXKwEE=; b=DMoht4cIEIQiqKA3yNQXgHTu5RLhszsz94bpsf5UYY1iQ8SqZrUzd5DdkBfW/Eyi9U swnwPXXkxzh7XUumG1GgTbq3kRQBLVUfYnktflM8P0YOzVWtJ59QV5/cSKGR+WRqXxGo y9Al33yfnF3xfp2AA7H1u8MNphiGPqETpsDp/rmGFbfbD9tDDp4IWdzvJ+1feKcOIbUW T8gKLKtYO6+bAv1zZTVRIkm/e/3EO0qxtR1rbTeySXolbb8Duud4dO1jEqnaROXljfYw l9cofT2Rneh/MvvYVOs6W3fDBNpFRY61cR6jJxCTKP5pPqs8mGWtptV9LHC+sfbO4Ifu 1XmA== X-Gm-Message-State: ANoB5pl9OLMnyoMw0CZEZAGEF+WMfje+Yrk3BjG16LaXohd3P0Vxy4mu B/dEqQD7Ki4bouEbS9QiYcex7Q== X-Google-Smtp-Source: AA0mqf4uoNtESHdzhp16/6ko0ItxfiZu0quayLxZD4UoKpS1Y/Tuw9fVd+KNhzvHX8Qelbqbvsb62A== X-Received: by 2002:a17:906:4e46:b0:7ae:129b:2d3a with SMTP id g6-20020a1709064e4600b007ae129b2d3amr3568516ejw.552.1668719045581; Thu, 17 Nov 2022 13:04:05 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:05 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 2/7] dt-bindings: irq: mtk, sysirq: add support for mt8365 Date: Thu, 17 Nov 2022 22:03:51 +0100 Message-Id: <20221117210356.3178578-3-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding documentation of mediatek,sysirq for mt8365 SoC. Signed-off-by: Bernhard Rosenkr=C3=A4nzer Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediate= k,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/media= tek,sysirq.txt index 84ced3f4179b9..3ffc60184e445 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysir= q.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysir= q.txt @@ -25,6 +25,7 @@ Required properties: "mediatek,mt6577-sysirq": for MT6577 "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.tx= t. - reg: Physical base address of the intpol registers and length of memory --=20 2.38.1 From nobody Sat Sep 21 09:47:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0854C433FE for ; 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Thu, 17 Nov 2022 13:04:06 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:06 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 3/7] dt-bindings: mfd: syscon: Add mt8365-syscfg Date: Thu, 17 Nov 2022 22:03:52 +0100 Message-Id: <20221117210356.3178578-4-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document Mediatek mt8365-syscfg Signed-off-by: Bernhard Rosenkr=C3=A4nzer Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 1b01bd0104316..7beeb0abc4db0 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -50,6 +50,7 @@ properties: - marvell,armada-3700-usb2-host-misc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep --=20 2.38.1 From nobody Sat Sep 21 09:47:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C97F0C4332F for ; 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Thu, 17 Nov 2022 13:04:07 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:06 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 4/7] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC Date: Thu, 17 Nov 2022 22:03:53 +0100 Message-Id: <20221117210356.3178578-5-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree bindings for Mediatek MT8365 pinctrl driver. Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt83= 65-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctr= l.yaml new file mode 100644 index 0000000000000..7758644da302a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkr=C3=A4nzer + +description: |+ + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + pins-are-numbered: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Specify the subnodes are using numbered pinmux to specify pins. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the= below + mentioned gpio binding representation for description of particular = cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + 'pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing = the + pinctrl groups available on the machine. Each subnode will list = the + pins it needs, and how they should be configured, with regard to= muxer + configuration, pullups, drive strength, input enable/disable and= input + schmitt. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and = are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pul= l up + settings for 2 pull resistors, R0 and R1. User can configure= those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only su= pport + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup= , they + can support 0.125/0.25/0.5/1mA adjustment. If we enable spec= ific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=3D0/E0=3D0, the strength is 0.125mA. + When E1=3D0/E0=3D1, the strength is 0.25mA. + When E1=3D1/E0=3D0, the strength is 0.5mA. + When E1=3D1/E0=3D1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) =3D (0, 0, 0) + 1: (E1, E0, EN) =3D (0, 0, 1) + 2: (E1, E0, EN) =3D (0, 1, 0) + 3: (E1, E0, EN) =3D (0, 1, 1) + 4: (E1, E0, EN) =3D (1, 0, 0) + 5: (E1, E0, EN) =3D (1, 0, 1) + 6: (E1, E0, EN) =3D (1, 1, 0) + 7: (E1, E0, EN) =3D (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described = as below: + 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. + 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. + 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. + 3: (R1, R0) =3D (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described = as below: + 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. + 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. + 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. + 3: (R1, R0) =3D (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arg= uments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty= cycle + when asserted (high pulse width adjustment). Valid arguments= are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + pio-pins { + pins { + pinmux =3D , ; + mediatek,pull-up-adv =3D <3>; + mediatek,drive-strength-adv =3D <00>; + bias-pull-up; + }; + }; + }; + }; --=20 2.38.1 From nobody Sat Sep 21 09:47:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF26AC433FE for ; Thu, 17 Nov 2022 21:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240648AbiKQVFg (ORCPT ); Thu, 17 Nov 2022 16:05:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240497AbiKQVEy (ORCPT ); Thu, 17 Nov 2022 16:04:54 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D4EE8E285 for ; Thu, 17 Nov 2022 13:04:12 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id ft34so8134401ejc.12 for ; Thu, 17 Nov 2022 13:04:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=psBkHMqowoOrMmAFezeNjkHyhvSdQLEEQY2n96pydj4=; b=lC07iQH1jl7tfyC4uuwpxN67tYK9v3Yjp9BvXxCSdX6Kr0gmCbNPBdwmbJH6C3IBqb soFQhNTCP7/AliDZ5iSeq0RwdGF+EzRCjT1LpsnXm7t/TYRvEi9oxspeX2RvrnzjoI3q kEguI2EWVejcIuEo6SqvkZl27KYYNVc5zDhOjp6G6X4eWHO/Py63/bOIiMBOknnmRlTV 8mQyuQ8AYKr2AN9DyT+F47KSk7ZPwz0WzSX+N6zLumlfhW7hxpwmXXEq4NHGzDce30In huAYYvKHB2gD2iq5gA9YryORcTIFpgxRadwCS7AJ5rG0mQLo9GGet5JFVsSOCr8hCbb1 IKQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=psBkHMqowoOrMmAFezeNjkHyhvSdQLEEQY2n96pydj4=; b=G9fLJQyBk+QuEmYb6VavgUnc37xDp1qVDDDRQfrlq2JGk9Zogb7uIUS8rbGfF5miSR n/tmi+lnKfQDAYB806BRs6iFit83FAARso+sKhG/iWVAdbYh3jeOt0z9UNg+bRuzBjLV FgnJH0P/e5LB4WQ2PuYqAUg2AKHf47iBllTBSMoOs329RdaJtCWhuhx+RnYYreA4YQjj RYMb5fdrqiFl4YZ5aseGtTmMWBN44WqcGjL9wF7XDGk9EHSpVeAtLmKlcYrY54mg+BpP Nh8UwPwPbrAjFHDQCQZ/Ky6M+piVklGOMA7zRW1V/vdRVkneWczLaMB0+zQjXp6xSGbm t28w== X-Gm-Message-State: ANoB5pm7exUhSbzVoz/Z9Ei+3FKh6gy0EqW4ASzGRLvaRFvwt9YvdPM9 a186uYJj6S/xNx69KzjklLxq2w== X-Google-Smtp-Source: AA0mqf61l4SIM8McX8K8sLWdW8glXhfskZ3bRupcaz7MKTOz5I2y9yCTpxnMADlL4hRsjV1FKMhlfQ== X-Received: by 2002:a17:906:5251:b0:791:9801:e48a with SMTP id y17-20020a170906525100b007919801e48amr3466134ejm.738.1668719048412; Thu, 17 Nov 2022 13:04:08 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:08 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 5/7] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings Date: Thu, 17 Nov 2022 22:03:54 +0100 Message-Id: <20221117210356.3178578-6-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Doc= umentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 80750b0f458a8..25934871a4d85 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 + - mediatek,mt8365-mtu3 - const: mediatek,mtu3 =20 reg: --=20 2.38.1 From nobody Sat Sep 21 09:47:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25E2AC4332F for ; Thu, 17 Nov 2022 21:05:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240790AbiKQVFm (ORCPT ); Thu, 17 Nov 2022 16:05:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240580AbiKQVE5 (ORCPT ); Thu, 17 Nov 2022 16:04:57 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AB1F905AB for ; Thu, 17 Nov 2022 13:04:12 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id z18so4386542edb.9 for ; Thu, 17 Nov 2022 13:04:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g6+ABKaCFT5+1C0Y5clbHMJQa6kjF8TIULfr4cCgl3o=; b=u4zUPtRBGTY9L9LHvnW9DqAWYRm0igVQllWoBz7XgHmcYSdMBuVAy58/lGWh4Dilqg 1UGWqw1Tezv5eZIYrQAdS5o5Y1q3ZB5f7z3i9FiJjFpOBmoKbUvRPlKrhKORJiYDLCA5 Pxu4VRIheLOlOvgE8Q7uWtouFjvgiuGkDdNjTP7dtEzfOp32WFKde4Sur0OYVYFhwHig ej/t/AXSZK8srV7eq50+nqPGqdyKShmDbKr5Vy2Pb5n1c1+TBEbgFx4xRQmV7BdicTpY 2McR2oldXKaFyZNjoYkZerusy/kP6ufcoRqtvQa+Fw+QK38iG4Ra7be2auIaioimyX+D xsjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g6+ABKaCFT5+1C0Y5clbHMJQa6kjF8TIULfr4cCgl3o=; b=629ajSaPBsYYoVIPR5KWovfn877Il+QJDSaJ1lrrpiEDfHdcG4sKdNy3uXykizeaXM Dk8eJtlVXXyLUg3KMjaeteyC7DBtLESMqndJ6PrIoDtLAwQasb5avM9MJZHssirR41wT y5XiG1NaSDYY1c+1NdL6ttbmOOG67Hp2XYzPqf8E+lnL1d0T/HxOtIDsltdFzlhbDN3s NqICKLPRNlyh9+lx0KRLHCR6BhZjogQ0p20RS6cAdj4i155YbNozSvWcO0nh4WwFjDHL M4XcAbizypyChqjyccwjdB5HNi7WQYu5tK+TeNiI+R8G4ePCUulyquwlpQJv9Zm9H6UB gNig== X-Gm-Message-State: ANoB5pl6kaeDfga5y52PBqWm7m7gsXjp7wBUBixFXaK/JW5pZN8bsbnz oU3lDQ/FaJdQAmYAF39MT4iMDg== X-Google-Smtp-Source: AA0mqf74WUgvaOJMRkg/rYttZ/P7xDEgL2yEBGs7v+osI383w3rkMb4HYPZYzRoe7OA5C12sjAKUGg== X-Received: by 2002:a05:6402:176c:b0:463:c5f7:fae with SMTP id da12-20020a056402176c00b00463c5f70faemr3583579edb.152.1668719049319; Thu, 17 Nov 2022 13:04:09 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:08 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 6/7] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings Date: Thu, 17 Nov 2022 22:03:55 +0100 Message-Id: <20221117210356.3178578-7-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b= /Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 939623867a646..3b92725bbc99b 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci =20 reg: --=20 2.38.1 From nobody Sat Sep 21 09:47:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E73D3C433FE for ; Thu, 17 Nov 2022 21:05:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240795AbiKQVFs (ORCPT ); Thu, 17 Nov 2022 16:05:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240432AbiKQVE7 (ORCPT ); Thu, 17 Nov 2022 16:04:59 -0500 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15F798D4B8 for ; Thu, 17 Nov 2022 13:04:14 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id bj12so8131489ejb.13 for ; Thu, 17 Nov 2022 13:04:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GAWtOLC8Z+7P6VnSdm6L5byyLB7u+ubRE7l02DZCq50=; b=7arb4tbJeiY6jaNIMSI/qq8Cfay0WR3evdPjW0nADnhX9oFpuFrZBXWsI5ngYkfH7Q GBzxcTdELDDR9mu/MfPh1253OCcoKnstO/EJn4u5x6SRBQskuo1sl1kN5u1jIgiUKO7J /yst8Yj7W8Y5LkwIzCCtiJ1BXwhy8bEQmmv9ehmfJTH1mvW/v7ABkyi7V8pAaU/CBnUv wX9lK2ilsJObsMoXi4L3p6ivalmmkGa7cvSVv/mlpINoaJxdIw5SI5LRYHAFXijHVAVC LWUmFusm0moAeY8n8RDMXBCIazrnJE10yq3sW0l12gRyRoELmC8hN5UkiXNQHJaaCGCf zL0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GAWtOLC8Z+7P6VnSdm6L5byyLB7u+ubRE7l02DZCq50=; b=fKveHgzPzEAA4i4BzCOxhWsc3lnYoeXE8kRxR+Rn8iwTf9scDejCjt3ua4bHOXEyPe YPfdc7QWyVMVe/OK6jYiXX3kaHi9m847HDoTkmg8iIQEOQcrPHvT0r0+MSLUJrCMY3QR zTsp04FTO4oiVv3aoD129VTs9UfTcxM8FWZ8XsGFTwDB/o2IymZaCpMOKHmpdklaYdfP Xp548/O11X8wzH9jq3a79CG1MqAt4+f6W0LxH1AsjMR8N0Q8ik1Ro4hB+Zw8ArvIz7og 2Q/AqokrriW+ybFXUAhTVZ445KuBLyNqAWXskllpWWiZx/1NxqcEAgB0Ky7bfx10R00l INUA== X-Gm-Message-State: ANoB5pllnbmOuuO8Wr+1pAd0XLrhKIwkSYyP7SOY1x+nB3rEXYST8DZ8 3fLRm5ZK3DBMb5H1YV5lBJJijw== X-Google-Smtp-Source: AA0mqf6S3oBB8bghlsQGmVaplIC5b5zK73p8+kdvRQ2208pa0WuYj4trxG81/R8hrDu4e/wIITZH5Q== X-Received: by 2002:a17:906:34d5:b0:7ae:b9fc:8668 with SMTP id h21-20020a17090634d500b007aeb9fc8668mr3341482ejb.257.1668719050422; Thu, 17 Nov 2022 13:04:10 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:09 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 7/7] arm64: dts: mediatek: Initial mt8365-evk support Date: Thu, 17 Nov 2022 22:03:56 +0100 Message-Id: <20221117210356.3178578-8-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent This adds minimal support for the Mediatek 8365 SOC and the EVK reference board, allowing the board to boot to initramfs with serial port I/O. Signed-off-by: Fabien Parent [bero@baylibre.com: Removed parts depending on drivers that aren't upstream= yet, cleanups, add L2 cache] Signed-off-by: Bernhard Rosenkr=C3=A4nzer Tested-by: Kevin Hilman --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 163 ++++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 344 ++++++++++++++++++++ 3 files changed, 508 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 0ec90cb3ef289..e668fd50a3326 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r2.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts new file mode 100644 index 0000000000000..972843f9e4e9d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent + * Bernhard Rosenkr=C3=A4nzer + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" + +/ { + model =3D "MediaTek MT8365 Open Platform EVK"; + compatible =3D "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + input-name =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys>; + + key-volume-up { + gpios =3D <&pio 24 GPIO_ACTIVE_LOW>; + label =3D "volume_up"; + linux,code =3D ; + wakeup-source; + debounce-interval =3D <15>; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "otg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg =3D <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&pio { + gpio_keys: gpio-keys-pins { + pins { + pinmux =3D ; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + }; + }; + + usb_pins: usb-pins { + pins-id { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-usb0-vbus { + pinmux =3D ; + output-high; + }; + + pin-usb1-vbus { + pinmux =3D ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux =3D , + ; + }; + }; +}; + +&pwm { + pinctrl-0 =3D <&pwm_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi new file mode 100644 index 0000000000000..64a77ce0a810d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent + * Bernhard Rosenkr=C3=A4nzer + */ +#include +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8365"; + interrupt-parent =3D <&sysirq>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache { + compatible =3D "cache"; + }; + }; + + clk26m: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg =3D <0 0x43000000 0 0x20000>; + }; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x80000>, <0 0x0c080000 0 0x80000>; + + interrupts =3D ; + }; + + topckgen: syscon@10000000 { + compatible =3D "mediatek,mt8365-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg: syscon@10001000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pericfg: syscon@10003000 { + compatible =3D "mediatek,mt8365-pericfg", "syscon"; + reg =3D <0 0x10003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible =3D "mediatek,mt8365-syscfg", "syscon"; + reg =3D <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + + apmixedsys: syscon@1000c000 { + compatible =3D "mediatek,mt8365-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + keypad: keypad@10010000 { + compatible =3D "mediatek,mt6779-keypad"; + reg =3D <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts =3D ; + clocks =3D <&clk26m>; + clock-names =3D "kpd"; + status =3D "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible =3D "mediatek,mt8365-mcucfg", "syscon"; + reg =3D <0 0x10200000 0 0x2000>; + #clock-cells =3D <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible =3D "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupt-parent =3D <&gic>; + reg =3D <0 0x10200a80 0 0x20>; + }; + + infracfg_nao: infracfg@1020e000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x1020e000 0 0x1000>; + }; + + rng: rng@1020f000 { + compatible =3D "mediatek,mt8365-rng", "mediatek,mt7623-rng"; + reg =3D <0 0x1020f000 0 0x100>; + clocks =3D <&infracfg CLK_IFR_TRNG>; + clock-names =3D "rng"; + }; + + apdma: dma-controller@11000280 { + compatible =3D "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; + reg =3D <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts =3D , + , + , + , + , + ; + dma-requests =3D <6>; + clocks =3D <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "apdma"; + #dma-cells =3D <1>; + }; + + uart0: serial@11002000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 0>, <&apdma 1>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart1: serial@11003000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 2>, <&apdma 3>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart2: serial@11004000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11004000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 4>, <&apdma 5>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + pwm: pwm@11006000 { + compatible =3D "mediatek,mt8365-pwm"; + reg =3D <0 0x11006000 0 0x1000>; + #pwm-cells =3D <2>; + interrupts =3D ; + clocks =3D <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names =3D "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + spi: spi@1100a000 { + compatible =3D "mediatek,mt8365-spi", "mediatek,mt7622-spi"; + reg =3D <0 0x1100a000 0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + ssusb: usb@11201000 { + compatible =3D "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host: usb@11200000 { + compatible =3D "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>; + reg-names =3D "mac"; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status =3D "disabled"; + }; + }; + + u3phy: phy@11cc0000 { + compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; + #address-cells =3D <2>; + #size-cells =3D <2>; + #phy-cells =3D <1>; + ranges; + + u2port0: usb-phy@11cc0000 { + reg =3D <0 0x11cc0000 0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + + u2port1: usb-phy@11cc1000 { + reg =3D <0 0x11cc1000 0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.38.1