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(fttx-pool-80.245.75.65.bambit.de [80.245.75.65]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id 18EA0100501; Thu, 17 Nov 2022 16:27:43 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Matthias Brugger , Paolo Abeni , Lorenzo Bianconi , Bo Jiao , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Sam Shih , Jieyy Yang , AngeloGioacchino Del Regno Subject: [PATCH v5 09/11] arm64: dts: mt7986: add pcie related device nodes Date: Thu, 17 Nov 2022 17:27:26 +0100 Message-Id: <20221117162728.20608-10-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117162728.20608-1-linux@fw-web.de> References: <20221117162728.20608-1-linux@fw-web.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: dfb25ea5-1a6e-4895-b22a-3994239809a8 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sam Shih This patch adds PCIe support for MT7986. Signed-off-by: Jieyy Yang Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- changes compared to sams original version: - add clock-names to pcie node - update clocks to new binding --- bindings-patches: https://patchwork.kernel.org/project/linux-mediatek/list/?series=3D690172 --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot= /dts/mediatek/mt7986a-rfb.dts index e1a0331aaa5f..01fa08c57c39 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -102,6 +102,15 @@ &mmc0 { non-removable; no-sd; no-sdio; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins>; + status =3D "okay"; +}; + +&pcie_phy { status =3D "okay"; }; =20 @@ -164,6 +173,13 @@ conf-rst { }; }; =20 + pcie_pins: pcie-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + spi_flash_pins: spi-flash-pins { mux { function =3D "spi"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7986a.dtsi index b3ad8978b563..b310abc02dcc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&gic>; @@ -319,6 +320,57 @@ mmc0: mmc@11230000 { status =3D "disabled"; }; =20 + pcie: pcie@11280000 { + compatible =3D "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x00 0x11280000 0x00 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x10000000>; + clocks =3D <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names =3D "pl_250m", "tl_26m", "peri_26m", "top_133m"; + status =3D "disabled"; + + phys =3D <&pcie_port PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + pcie_phy: t-phy@11c00000 { + compatible =3D "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + pcie_port: pcie-phy@11c00000 { + reg =3D <0 0x11c00000 0 0x20000>; + clocks =3D <&clk40m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + usb_phy: t-phy@11e10000 { compatible =3D "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; --=20 2.34.1