From nobody Wed Apr 15 18:12:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8D03C4332F for ; Thu, 17 Nov 2022 11:37:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239526AbiKQLhU (ORCPT ); Thu, 17 Nov 2022 06:37:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239739AbiKQLgw (ORCPT ); Thu, 17 Nov 2022 06:36:52 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 129306B227 for ; Thu, 17 Nov 2022 03:36:48 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id bj12so4230257ejb.13 for ; Thu, 17 Nov 2022 03:36:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ROWbtxy/soEJAKDSGVx/bebkoFFFAxHo/Tr5JwjJoOE=; b=OzcPBlTdwYYpvStvhdyIE4v8lSCGqx4NTZAf8CHiS+DxmIaZswowqueqqC1oVX7uwI bqRpowGJDGjBJlcFQOI/Te/bs1kjGi/XgZ2lcEr67KpmpT/TK594fqwgY3ivGizpoQ/7 v5rW6SYMJHQYkexPR0UoU2ZSs+X3dmAqK3CFY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ROWbtxy/soEJAKDSGVx/bebkoFFFAxHo/Tr5JwjJoOE=; b=JKzklufa5QrK/pQDuh9DjmzL4eHEChgXEMGKk3hJDw8yOtIHY5VNGhDX+bPD8G8L3O jVrnPwWkZjRi4nau5XsNx4+OZ2+Xb/oiKdGyq42eLR6osB97np+e9FVr9BXkp5Olx+4P M4y2V/+ERMQSi3yIj6UQ/E1TFoF8NeCi5Xo6nSB89N+iFkR30lg0o5jYnCBlMCfYZy88 AM2I3NDMH6+vECUPUOXenc3xUh0zCNgX9INbFR0aWZE3JYxNvmjCBLuIbr7aPwEs81rG DOqtMRXB9++BgVwRnTdEX6PgT/HgfBEvaRxF/lUFHcv1mE61+8NCHXK7bFkVmfAIrWzz Eu4A== X-Gm-Message-State: ANoB5pn8GFc5f/aDsTCLBQ8QRzKjg3SjIbjMCdhOBDAG7wvPvwbOCGeQ NWebkD4jixf71527XLHsdrXLaygqITLbVw== X-Google-Smtp-Source: AA0mqf4jk37GR4exGvAv3TAisKlh0zjl7VEEDeYnV1QrPAbVdhyH04djR+9Nkn2O5e8iK/JrkTJDbQ== X-Received: by 2002:a17:906:1182:b0:78d:99f2:a94e with SMTP id n2-20020a170906118200b0078d99f2a94emr1805874eja.232.1668685006404; Thu, 17 Nov 2022 03:36:46 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (mob-5-90-137-239.net.vodafone.it. [5.90.137.239]) by smtp.gmail.com with ESMTPSA id g3-20020aa7c843000000b0043bbb3535d6sm413897edt.66.2022.11.17.03.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 03:36:46 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Anson Huang , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 1/5] clk: imx8mn: rename vpu_pll to m7_alt_pll Date: Thu, 17 Nov 2022 12:36:33 +0100 Message-Id: <20221117113637.1978703-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> References: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The IMX8MN platform does not have any video processing unit (VPU), and indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there is no occurrence of its pll. From an analysis of the code and the RM itself, I think vpu pll is used instead of m7 alternate pll, probably for copy and paste of code taken from modules of similar architectures. As an example for all, if we consider the second row of the "Clock Root" table of chapter 5 (Clocks and Power Management) of the RM: Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ARM_M7_CLK_ROOT 0x8080 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV5 010 - SYSTEM_PLL2_DIV4 011 - M7_ALT_PLL_CLK 100 - SYSTEM_PLL1_CLK 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - SYSTEM_PLL3_CLK ... ... ... but in the source code, the imx8mn_m7_sels clocks list contains vpu_pll for the source select bits 011b. So, let's rename "vpu_pll" to "m7_alt_pll" to be consistent with the RM. The IMX8MN_VPU_* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Reviewed-by: Abel Vesa --- Changes in v2: - Update the commit message. - Add Fixes tag. - Maintain IMX8MN_VPU_* constants to not break backward compatibility. drivers/clk/imx/clk-imx8mn.c | 16 ++++++++-------- include/dt-bindings/clock/imx8mn-clock.h | 12 ++++++++---- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index d37c45b676ab..72f9563a0ff6 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -30,7 +30,7 @@ static const char * const audio_pll2_bypass_sels[] =3D {"= audio_pll2", "audio_pll2_ static const char * const video_pll1_bypass_sels[] =3D {"video_pll1", "vid= eo_pll1_ref_sel", }; static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; -static const char * const vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_r= ef_sel", }; +static const char * const m7_alt_pll_bypass_sels[] =3D {"m7_alt_pll", "m7_= alt_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; =20 @@ -40,7 +40,7 @@ static const char * const imx8mn_a53_sels[] =3D {"osc_24m= ", "arm_pll_out", "sys_pl =20 static const char * const imx8mn_a53_core_sels[] =3D {"arm_a53_div", "arm_= pll_out", }; =20 -static const char * const imx8mn_m7_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_250m", "vpu_pll_out", +static const char * const imx8mn_m7_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_250m", "m7_alt_pll_out", "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_= out", }; =20 static const char * const imx8mn_gpu_core_sels[] =3D {"osc_24m", "gpu_pll_= out", "sys_pll1_800m", @@ -252,10 +252,10 @@ static const char * const imx8mn_gpt6_sels[] =3D {"os= c_24m", "sys_pll2_100m", "sys "audio_pll1_out", "clk_ext1", }; =20 static const char * const imx8mn_wdog_sels[] =3D {"osc_24m", "sys_pll1_133= m", "sys_pll1_160m", - "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", + "m7_alt_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; =20 -static const char * const imx8mn_wrclk_sels[] =3D {"osc_24m", "sys_pll1_40= m", "vpu_pll_out", +static const char * const imx8mn_wrclk_sels[] =3D {"osc_24m", "sys_pll1_40= m", "m7_alt_pll_out", "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", }; =20 @@ -352,7 +352,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) hws[IMX8MN_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", b= ase + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", base + = 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_clk_hw_mux("m7_alt_pll_ref_sel", b= ase + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 @@ -361,7 +361,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) hws[IMX8MN_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", base + 0x28, &imx_1443x_pll); hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); - hws[IMX8MN_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = base + 0x74, &imx_1416x_pll); + hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", base + 0x74, &imx_1416x_pll); hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); hws[IMX8MN_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); hws[IMX8MN_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); @@ -373,7 +373,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) hws[IMX8MN_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass= _sels), CLK_SET_RATE_PARENT); hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", bas= e + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); + hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_clk_hw_mux_flags("m7_alt_pll_bypass= ", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass= _sels), CLK_SET_RATE_PARENT); hws[IMX8MN_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", bas= e + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_= SET_RATE_PARENT); hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", b= ase + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),= CLK_SET_RATE_PARENT); =20 @@ -383,7 +383,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) hws[IMX8MN_VIDEO_PLL1_OUT] =3D imx_clk_hw_gate("video_pll1_out", "video_p= ll1_bypass", base + 0x28, 13); hws[IMX8MN_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); hws[IMX8MN_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); - hws[IMX8MN_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", base + 0x74, 11); + hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_= pll_bypass", base + 0x74, 11); hws[IMX8MN_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", base + 0x84, 11); hws[IMX8MN_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", base + 0x114, 11); =20 diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings= /clock/imx8mn-clock.h index 07b8a282c268..694e3c050d04 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -19,7 +19,8 @@ #define IMX8MN_VIDEO_PLL1_REF_SEL 10 #define IMX8MN_DRAM_PLL_REF_SEL 11 #define IMX8MN_GPU_PLL_REF_SEL 12 -#define IMX8MN_VPU_PLL_REF_SEL 13 +#define IMX8MN_M7_ALT_PLL_REF_SEL 13 +#define IMX8MN_VPU_PLL_REF_SEL IMX8MN_M7_ALT_PLL_REF_SEL #define IMX8MN_ARM_PLL_REF_SEL 14 #define IMX8MN_SYS_PLL1_REF_SEL 15 #define IMX8MN_SYS_PLL2_REF_SEL 16 @@ -29,7 +30,8 @@ #define IMX8MN_VIDEO_PLL1 20 #define IMX8MN_DRAM_PLL 21 #define IMX8MN_GPU_PLL 22 -#define IMX8MN_VPU_PLL 23 +#define IMX8MN_M7_ALT_PLL 23 +#define IMX8MN_VPU_PLL IMX8MN_M7_ALT_PLL #define IMX8MN_ARM_PLL 24 #define IMX8MN_SYS_PLL1 25 #define IMX8MN_SYS_PLL2 26 @@ -39,7 +41,8 @@ #define IMX8MN_VIDEO_PLL1_BYPASS 30 #define IMX8MN_DRAM_PLL_BYPASS 31 #define IMX8MN_GPU_PLL_BYPASS 32 -#define IMX8MN_VPU_PLL_BYPASS 33 +#define IMX8MN_M7_ALT_PLL_BYPASS 33 +#define IMX8MN_VPU_PLL_BYPASS IMX8MN_M7_ALT_PLL_BYPASS #define IMX8MN_ARM_PLL_BYPASS 34 #define IMX8MN_SYS_PLL1_BYPASS 35 #define IMX8MN_SYS_PLL2_BYPASS 36 @@ -49,7 +52,8 @@ #define IMX8MN_VIDEO_PLL1_OUT 40 #define IMX8MN_DRAM_PLL_OUT 41 #define IMX8MN_GPU_PLL_OUT 42 -#define IMX8MN_VPU_PLL_OUT 43 +#define IMX8MN_M7_ALT_PLL_OUT 43 +#define IMX8MN_VPU_PLL_OUT IMX8MN_M7_ALT_PLL_OUT #define IMX8MN_ARM_PLL_OUT 44 #define IMX8MN_SYS_PLL1_OUT 45 #define IMX8MN_SYS_PLL2_OUT 46 --=20 2.32.0 From nobody Wed Apr 15 18:12:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BF75C4332F for ; Thu, 17 Nov 2022 11:37:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239160AbiKQLh0 (ORCPT ); Thu, 17 Nov 2022 06:37:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239622AbiKQLgw (ORCPT ); Thu, 17 Nov 2022 06:36:52 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42FD0697CD for ; Thu, 17 Nov 2022 03:36:51 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id z18so2097126edb.9 for ; Thu, 17 Nov 2022 03:36:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yxMfjMiirY7i5b76cAjsj02YyQXT341SCmcBph5Qf+U=; b=N3eCNDBEJ+8l57N4d/x9r6FkVKlS2jcl6LFxZauI6rZhfJUbwC5ZX6bCZ5TnSTxqAk dorvUmZJmgAC7mZT+0cjBrimIQjcxsvRgJeTFZndPyO/3+ZSAJBUw18HBwqkCYqrwOB1 HdIbVpR/Uof0e9HNc+o4Dm2E9mXQlmsB+3mHU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yxMfjMiirY7i5b76cAjsj02YyQXT341SCmcBph5Qf+U=; b=amZQE9z83x62zkCxp+rgv4Bat6Z8FByUeGRcnjgrc6EelPwg8zuym0G+5gAwqzi3fR d0RvIokMv90+05LvsjeEc0PDRq/kNzba3zB0ZJN/VmBRz3Lb4TRLLrzTHGCiYmOH3AcU D4LHkJRCUGwbSd+adlAg2bLl5T72aTB/kgOxwnuSYcmxD4CoZTqwmGOP+6TiwbNgsnop ZQrk29aeqlIB2xgghssDuazjGOeNKSfSlcJmtAWc6/u96WlFamOlcBf2jLAyOmiMEoRQ d5dtu1f6MUDZFIE3ZiNgL0GcjAnVjNzMiYgi1ufcynwX59gvRipz8rSOX46gAZhV3WBq e5iQ== X-Gm-Message-State: ANoB5plER8gy+FVjWOKtAC7GgnDLnD/39EMJiczvdCw1PqOFMaiDTpXx WeUYLI8ohDiCdjalKXfxEOlSNtqx/PzNwQ== X-Google-Smtp-Source: AA0mqf4LwN9I4lHe7fW0Tr4dbP1il3VAcVtfsnSz+I+H23yl+dOsCGmSKJh/Doj5kWYPVAzkeE7dlQ== X-Received: by 2002:a05:6402:1399:b0:461:53b0:2ac0 with SMTP id b25-20020a056402139900b0046153b02ac0mr1740983edv.153.1668685009735; Thu, 17 Nov 2022 03:36:49 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (mob-5-90-137-239.net.vodafone.it. [5.90.137.239]) by smtp.gmail.com with ESMTPSA id g3-20020aa7c843000000b0043bbb3535d6sm413897edt.66.2022.11.17.03.36.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 03:36:49 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Anson Huang , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/5] clk: imx: replace osc_hdmi with dummy Date: Thu, 17 Nov 2022 12:36:34 +0100 Message-Id: <20221117113637.1978703-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> References: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is no occurrence of the hdmi oscillator in the reference manual (document IMX8MNRM Rev 2, 07/2022). Further, if we consider the indexes 76-81 and 134 of the "Clock Root" table of chapter 5 of the RM, there is no entry for the source select bits 101b, which is the setting referenced by "osc_hdmi". Fix by renaming "osc_hdmi" with "dummy", a clock which has already been used for missing source select bits. Tested on the BSH SystemMaster (SMM) S2 board. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch --- (no changes since v1) drivers/clk/imx/clk-imx8mn.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 72f9563a0ff6..0fae97e61e2c 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -108,27 +108,27 @@ static const char * const imx8mn_disp_pixel_sels[] = =3D {"osc_24m", "video_pll1_out "sys_pll3_out", "clk_ext4", }; =20 static const char * const imx8mn_sai2_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mn_sai3_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mn_sai5_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mn_sai6_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mn_sai7_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mn_spdif1_sels[] =3D {"osc_24m", "audio_pll1= _out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll1_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mn_enet_ref_sels[] =3D {"osc_24m", "sys_pll2= _125m", "sys_pll2_50m", --=20 2.32.0 From nobody Wed Apr 15 18:12:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07F22C433FE for ; Thu, 17 Nov 2022 11:37:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239764AbiKQLhb (ORCPT ); Thu, 17 Nov 2022 06:37:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239716AbiKQLg4 (ORCPT ); Thu, 17 Nov 2022 06:36:56 -0500 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD7FE67F75 for ; Thu, 17 Nov 2022 03:36:53 -0800 (PST) Received: by mail-ej1-x630.google.com with SMTP id f18so4349436ejz.5 for ; Thu, 17 Nov 2022 03:36:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rl6wZCAHM6P6IFwXGM/MR+ypnVw95L969SDFtD13ca0=; b=ozxzcdyD90On+2gTxP5SUgO5llMd2R6w0uGmvYJP98NuOQ0S9G/4M4toM+M5XI/mQw ZidgObGOTsKCDBAVmWb6GIdl2iigZyM5erPMqTx01cEUGJHHzO209sntd2MCA59bEcpP cJGqH2DlDBpz6mlWyk4sX/ZjuEXvCP/IDjeIk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rl6wZCAHM6P6IFwXGM/MR+ypnVw95L969SDFtD13ca0=; b=zUOzY5h+JpofMsqCUKTj8URf3K8xhpLSY+FRZKg2N1Oddatbnh/iPHJsVrwuIWuKay zkSD84byvebC23a0kfUR+RaV1gSQWbezU6Ud4A8rLh2yI6s4iWuQSXGOVEW177f/wFOr kM6l4VTOD3Y7sOmwd4gMmUPDZ7BGkWDZzdHZeKdUD9UXgIX+VoVD+sQjpanyOXLeOBQM oGTxaYFa5SdKHrnbdLNx1eTdYVBfuurPEklsPKaB8Hk3Tl21u5pihjU7bqUXt7tqCwjv tWlxwm6mxmvYgTmP3YcokGYbGhyCRJpDhGpbzDedceCaGFWkEuFqGeFerqvtsXdexd3H 1C5g== X-Gm-Message-State: ANoB5pnmN3LOQKvwTRBnwibVxZy2UQqwgi+x0Rr9xWLH8SNnXZ6vXHEF JMpKhUsiHRDTPB+y9/wenRHlU7T/TV9SSQ== X-Google-Smtp-Source: AA0mqf7kCdYsnpf/wlpecleW1xbZzFekkAt075piUcAc0HL5sNuqoSDI7E7pMUxCMuk5VxvbZEFRQw== X-Received: by 2002:a17:906:b210:b0:7ae:d116:fabb with SMTP id p16-20020a170906b21000b007aed116fabbmr1744882ejz.317.1668685011937; Thu, 17 Nov 2022 03:36:51 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (mob-5-90-137-239.net.vodafone.it. [5.90.137.239]) by smtp.gmail.com with ESMTPSA id g3-20020aa7c843000000b0043bbb3535d6sm413897edt.66.2022.11.17.03.36.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 03:36:51 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Anson Huang , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 3/5] clk: imx: rename video_pll1 to video_pll Date: Thu, 17 Nov 2022 12:36:35 +0100 Message-Id: <20221117113637.1978703-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> References: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. The IMX8MN_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Reviewed-by: Abel Vesa --- Changes in v2: - Update the commit message. - Add Fixes tag. - Maintain IMX8MN_VIDEO_PLL1* constants to not break backward compatibility. drivers/clk/imx/clk-imx8mn.c | 96 ++++++++++++------------ include/dt-bindings/clock/imx8mn-clock.h | 12 ++- 2 files changed, 56 insertions(+), 52 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 0fae97e61e2c..b80af5d1ef46 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -27,7 +27,7 @@ static u32 share_count_nand; static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; -static const char * const video_pll1_bypass_sels[] =3D {"video_pll1", "vid= eo_pll1_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; static const char * const m7_alt_pll_bypass_sels[] =3D {"m7_alt_pll", "m7_= alt_pll_ref_sel", }; @@ -41,23 +41,23 @@ static const char * const imx8mn_a53_sels[] =3D {"osc_2= 4m", "arm_pll_out", "sys_pl static const char * const imx8mn_a53_core_sels[] =3D {"arm_a53_div", "arm_= pll_out", }; =20 static const char * const imx8mn_m7_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_250m", "m7_alt_pll_out", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_= out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_o= ut", }; =20 static const char * const imx8mn_gpu_core_sels[] =3D {"osc_24m", "gpu_pll_= out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mn_gpu_shader_sels[] =3D {"osc_24m", "gpu_pl= l_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mn_main_axi_sels[] =3D {"osc_24m", "sys_pll2= _333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "sys_pll1_100m",}; + "video_pll_out", "sys_pll1_100m",}; =20 static const char * const imx8mn_enet_axi_sels[] =3D {"osc_24m", "sys_pll1= _266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; =20 static const char * const imx8mn_nand_usdhc_sels[] =3D {"osc_24m", "sys_pl= l1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", @@ -77,23 +77,23 @@ static const char * const imx8mn_usb_bus_sels[] =3D {"o= sc_24m", "sys_pll2_500m", " =20 static const char * const imx8mn_gpu_axi_sels[] =3D {"osc_24m", "sys_pll1_= 800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mn_gpu_ahb_sels[] =3D {"osc_24m", "sys_pll1_= 800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mn_noc_sels[] =3D {"osc_24m", "sys_pll1_800m= ", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mn_ahb_sels[] =3D {"osc_24m", "sys_pll1_133m= ", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mn_audio_ahb_sels[] =3D {"osc_24m", "sys_pll= 2_500m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mn_dram_alt_sels[] =3D {"osc_24m", "sys_pll1= _800m", "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", @@ -103,49 +103,49 @@ static const char * const imx8mn_dram_apb_sels[] =3D = {"osc_24m", "sys_pll2_200m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; =20 -static const char * const imx8mn_disp_pixel_sels[] =3D {"osc_24m", "video_= pll1_out", "audio_pll2_out", +static const char * const imx8mn_disp_pixel_sels[] =3D {"osc_24m", "video_= pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 static const char * const imx8mn_sai2_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mn_sai3_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mn_sai5_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mn_sai6_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mn_sai7_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mn_spdif1_sels[] =3D {"osc_24m", "audio_pll1= _out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "dummy", + "video_pll_out", "sys_pll1_133m", "dummy", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mn_enet_ref_sels[] =3D {"osc_24m", "sys_pll2= _125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; =20 static const char * const imx8mn_enet_timer_sels[] =3D {"osc_24m", "sys_pl= l2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; =20 static const char * const imx8mn_enet_phy_sels[] =3D {"osc_24m", "sys_pll2= _50m", "sys_pll2_125m", - "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out", + "sys_pll2_200m", "sys_pll2_500m", "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mn_nand_sels[] =3D {"osc_24m", "sys_pll2_500= m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", - "sys_pll2_250m", "video_pll1_out", }; + "sys_pll2_250m", "video_pll_out", }; =20 static const char * const imx8mn_qspi_sels[] =3D {"osc_24m", "sys_pll1_400= m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", @@ -160,19 +160,19 @@ static const char * const imx8mn_usdhc2_sels[] =3D {"= osc_24m", "sys_pll1_400m", "s "audio_pll2_out", "sys_pll1_100m", }; =20 static const char * const imx8mn_i2c1_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mn_i2c2_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mn_i2c3_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mn_i2c4_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mn_uart1_sels[] =3D {"osc_24m", "sys_pll1_80= m", "sys_pll2_200m", @@ -213,42 +213,42 @@ static const char * const imx8mn_ecspi2_sels[] =3D {"= osc_24m", "sys_pll2_200m", "s =20 static const char * const imx8mn_pwm1_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mn_pwm2_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mn_pwm3_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mn_pwm4_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mn_gpt1_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; =20 static const char * const imx8mn_gpt2_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; =20 static const char * const imx8mn_gpt3_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; =20 static const char * const imx8mn_gpt4_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; =20 static const char * const imx8mn_gpt5_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; =20 static const char * const imx8mn_gpt6_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1", }; =20 static const char * const imx8mn_wdog_sels[] =3D {"osc_24m", "sys_pll1_133= m", "sys_pll1_160m", @@ -261,15 +261,15 @@ static const char * const imx8mn_wrclk_sels[] =3D {"o= sc_24m", "sys_pll1_40m", "m7_ =20 static const char * const imx8mn_dsi_core_sels[] =3D {"osc_24m", "sys_pll1= _266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mn_dsi_phy_sels[] =3D {"osc_24m", "sys_pll2_= 125m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mn_dsi_dbi_sels[] =3D {"osc_24m", "sys_pll1_= 266m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mn_usdhc3_sels[] =3D {"osc_24m", "sys_pll1_4= 00m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", @@ -277,15 +277,15 @@ static const char * const imx8mn_usdhc3_sels[] =3D {"= osc_24m", "sys_pll1_400m", "s =20 static const char * const imx8mn_camera_pixel_sels[] =3D {"osc_24m", "sys_= pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mn_csi1_phy_sels[] =3D {"osc_24m", "sys_pll2= _333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mn_csi2_phy_sels[] =3D {"osc_24m", "sys_pll2= _333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mn_csi2_esc_sels[] =3D {"osc_24m", "sys_pll2= _100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", @@ -306,9 +306,9 @@ static const char * const imx8mn_clko1_sels[] =3D {"osc= _24m", "sys_pll1_800m", "du "dummy", "sys_pll1_80m", }; static const char * const imx8mn_clko2_sels[] =3D {"osc_24m", "sys_pll2_20= 0m", "sys_pll1_400m", "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "osc_32k", }; + "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll1_out", +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "dummy", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -349,7 +349,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", b= ase + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_clk_hw_mux("m7_alt_pll_ref_sel", b= ase + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -358,7 +358,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", base + 0x28, &imx_1443x_pll); + hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", base + 0x74, &imx_1416x_pll); @@ -370,7 +370,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) /* PLL bypass out */ hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass= _sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_clk_hw_mux_flags("m7_alt_pll_bypass= ", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass= _sels), CLK_SET_RATE_PARENT); @@ -380,7 +380,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) /* PLL out gate */ hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL1_OUT] =3D imx_clk_hw_gate("video_pll1_out", "video_p= ll1_bypass", base + 0x28, 13); + hws[IMX8MN_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); hws[IMX8MN_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); hws[IMX8MN_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_= pll_bypass", base + 0x74, 11); diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings= /clock/imx8mn-clock.h index 694e3c050d04..04809edab33c 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -16,7 +16,8 @@ #define IMX8MN_CLK_EXT4 7 #define IMX8MN_AUDIO_PLL1_REF_SEL 8 #define IMX8MN_AUDIO_PLL2_REF_SEL 9 -#define IMX8MN_VIDEO_PLL1_REF_SEL 10 +#define IMX8MN_VIDEO_PLL_REF_SEL 10 +#define IMX8MN_VIDEO_PLL1_REF_SEL IMX8MN_VIDEO_PLL_REF_SEL #define IMX8MN_DRAM_PLL_REF_SEL 11 #define IMX8MN_GPU_PLL_REF_SEL 12 #define IMX8MN_M7_ALT_PLL_REF_SEL 13 @@ -27,7 +28,8 @@ #define IMX8MN_SYS_PLL3_REF_SEL 17 #define IMX8MN_AUDIO_PLL1 18 #define IMX8MN_AUDIO_PLL2 19 -#define IMX8MN_VIDEO_PLL1 20 +#define IMX8MN_VIDEO_PLL 20 +#define IMX8MN_VIDEO_PLL1 IMX8MN_VIDEO_PLL #define IMX8MN_DRAM_PLL 21 #define IMX8MN_GPU_PLL 22 #define IMX8MN_M7_ALT_PLL 23 @@ -38,7 +40,8 @@ #define IMX8MN_SYS_PLL3 27 #define IMX8MN_AUDIO_PLL1_BYPASS 28 #define IMX8MN_AUDIO_PLL2_BYPASS 29 -#define IMX8MN_VIDEO_PLL1_BYPASS 30 +#define IMX8MN_VIDEO_PLL_BYPASS 30 +#define IMX8MN_VIDEO_PLL1_BYPASS IMX8MN_VIDEO_PLL_BYPASS #define IMX8MN_DRAM_PLL_BYPASS 31 #define IMX8MN_GPU_PLL_BYPASS 32 #define IMX8MN_M7_ALT_PLL_BYPASS 33 @@ -49,7 +52,8 @@ #define IMX8MN_SYS_PLL3_BYPASS 37 #define IMX8MN_AUDIO_PLL1_OUT 38 #define IMX8MN_AUDIO_PLL2_OUT 39 -#define IMX8MN_VIDEO_PLL1_OUT 40 +#define IMX8MN_VIDEO_PLL_OUT 40 +#define IMX8MN_VIDEO_PLL1_OUT IMX8MN_VIDEO_PLL_OUT #define IMX8MN_DRAM_PLL_OUT 41 #define IMX8MN_GPU_PLL_OUT 42 #define IMX8MN_M7_ALT_PLL_OUT 43 --=20 2.32.0 From nobody Wed Apr 15 18:12:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26CBFC433FE for ; Thu, 17 Nov 2022 11:37:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239787AbiKQLhh (ORCPT ); Thu, 17 Nov 2022 06:37:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239742AbiKQLg4 (ORCPT ); Thu, 17 Nov 2022 06:36:56 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E307697F0 for ; Thu, 17 Nov 2022 03:36:55 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id t25so4301231ejb.8 for ; Thu, 17 Nov 2022 03:36:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1SFs+QuCEjvSeA5k7rG5hAilinvi7WiyttbklMW+zRY=; b=HAScRzzTzMiwVuHheDpDzRDi1KBTMXnthhKUw5f+srNRN3JRZeL2EZZBx4TXbkJS/C 8EBoHuVzhnZTEcDdoLO9cnSv0GYIch6WGLucnPEQFQerTGfTxBJ3m4IIod/EZ6cWLBtH XYC4RSnUx0SkkHvuzOjJfQ0xyS7WEQ3dQ0ED4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1SFs+QuCEjvSeA5k7rG5hAilinvi7WiyttbklMW+zRY=; b=5dzT3g7Et9BG77peGvwWuth/mjkgNCxXuw6uJ3VfmN+WGXaLGsfrHbaVKgA70K8feY zIQpwvk6vGpsMRO8qi31O5ij9Kg0IOyW2xycDPjDAdKQ2jjz7rsVdJgg0n+1eSH+A1QB Pe/wQfZhRefP95bQUqypRel7C3KhE/WYyA7Wg7tJ970JDAG5tgOhB1uaMWP2C/V7shm2 GebrqBPHyWCEXoKQkBzusYtRby4MzPitZI8zUsObrKxDV8yigD0MZK6u3t3XiUZk8NZy BJ/hS1NCT0thTkGNKZ5rMjBteJokbRFA+yDHlgVgTN9Y8VFZpOJVyfs6qcInqOiB2WZM 4hyg== X-Gm-Message-State: ANoB5plH7yD3zvkqc54tubuCl43x00P6XaRtI1LZ3QlQBMoZ2aq6ScUc OkHYdL1ttJbB9s3znyf30Nhnr/VBpY6QzA== X-Google-Smtp-Source: AA0mqf4K7r/gLLF24KW0FjHrDSx3N1e7ptvm4Bq2Kgwmep/3Tt6m1SOa7CMxe9/PFzl5etBPl3NN5Q== X-Received: by 2002:a17:906:15ca:b0:7a5:7c1c:cc5c with SMTP id l10-20020a17090615ca00b007a57c1ccc5cmr1779224ejd.644.1668685013753; Thu, 17 Nov 2022 03:36:53 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (mob-5-90-137-239.net.vodafone.it. [5.90.137.239]) by smtp.gmail.com with ESMTPSA id g3-20020aa7c843000000b0043bbb3535d6sm413897edt.66.2022.11.17.03.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 03:36:53 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Anson Huang , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 4/5] clk: imx8mn: fix imx8mn_sai2_sels clocks list Date: Thu, 17 Nov 2022 12:36:36 +0100 Message-Id: <20221117113637.1978703-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> References: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... SAI2_CLK_ROOT 0xA600 000 - 24M_REF_CLK 001 - AUDIO_PLL1_CLK 010 - AUDIO_PLL2_CLK 011 - VIDEO_PLL_CLK 100 - SYSTEM_PLL1_DIV6 110 - EXT_CLK_2 111 - EXT_CLK_3 ... ... ... while the imx8mn_sai2_sels list contained clk_ext3 and clk_ext4 for source select bits 110b and 111b. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Reviewed-by: Abel Vesa --- (no changes since v1) drivers/clk/imx/clk-imx8mn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index b80af5d1ef46..37128c35198d 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -109,7 +109,7 @@ static const char * const imx8mn_disp_pixel_sels[] =3D = {"osc_24m", "video_pll_out" =20 static const char * const imx8mn_sai2_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "dummy", - "clk_ext3", "clk_ext4", }; + "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mn_sai3_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "dummy", --=20 2.32.0 From nobody Wed Apr 15 18:12:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7407CC4332F for ; Thu, 17 Nov 2022 11:37:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239798AbiKQLhn (ORCPT ); Thu, 17 Nov 2022 06:37:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239770AbiKQLg5 (ORCPT ); Thu, 17 Nov 2022 06:36:57 -0500 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C8EC6A748 for ; Thu, 17 Nov 2022 03:36:57 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id n21so4292503ejb.9 for ; Thu, 17 Nov 2022 03:36:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V3uDGf6nFwfo97/RpmImJcIh+Hx1nK4UXLWDjOMYdaw=; b=nghdVoejMDXntacsNMzk02oYdAH1coNLAAX6KPeORBPUIb7lccM+HohiaZmwdB2xZ1 qac0MMxDTK5WP7KQm2UBZo6UIF+7tOl+tJdtpwkKqOY9Usr8o/1zqlliEgeW9s7qCbUz VxVHop7EHwDiK1nJknM04XVO07/dBquGZN3fY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V3uDGf6nFwfo97/RpmImJcIh+Hx1nK4UXLWDjOMYdaw=; b=s6+39Ov67En24b07MED3j3SXoHAAEHr2Kh06Fe3Fb1Oqg0JLx3NxLMmJbPS9ntd/D+ AjPkQesqaJ1foc6XmVmhN4BucvC0x1FqSo06Tgtq8v50GYtmV34y9tt1mCdeIXIXVNvj ll3Ahn0A3o1ZqeUEsiJ8h1t5qaYFFcUt+MP3zhIPx05ki+aSi+18aA5CKEW+DDdvRuyQ BPOD6Ej31fce9hT2HGdCNFD4wd0Hkiu45CIdcSf4i68QX51CENo66wpPr3ppqaHyuHve u/vwdc7QFGNAL6eE+WFQIg43eM0bz+uvYw/4oZaYCbCkZM6ucBuRXPYXZC0DJ6C+3U+V asvQ== X-Gm-Message-State: ANoB5pncNFjD+Wd8BRWcEsSMhCnj76qY11O/ZByzM/L0f0B+xGYVqTeD UCmLbzDcmP1e72xKO8UQh/naV9emEor6Uw== X-Google-Smtp-Source: AA0mqf69VIOyLwRRt2pkjgSAuCU7OJ+nTpFybk4c/13Qw5Eo+FsO7QNm+AvpwZWJ2r8izt+7M0uwTg== X-Received: by 2002:a17:906:49c2:b0:7aa:23ac:608e with SMTP id w2-20020a17090649c200b007aa23ac608emr1738874ejv.450.1668685015577; Thu, 17 Nov 2022 03:36:55 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (mob-5-90-137-239.net.vodafone.it. [5.90.137.239]) by smtp.gmail.com with ESMTPSA id g3-20020aa7c843000000b0043bbb3535d6sm413897edt.66.2022.11.17.03.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 03:36:55 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Anson Huang , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 5/5] clk: imx8mn: fix imx8mn_enet_phy_sels clocks list Date: Thu, 17 Nov 2022 12:36:37 +0100 Message-Id: <20221117113637.1978703-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> References: <20221117113637.1978703-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV20 010 - SYSTEM_PLL2_DIV8 011 - SYSTEM_PLL2_DIV5 100 - SYSTEM_PLL2_DIV2 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - AUDIO_PLL2_CLK ... ... ... while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for source select bits 101b. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi Acked-by: Marco Felsch Reviewed-by: Abel Vesa --- (no changes since v1) drivers/clk/imx/clk-imx8mn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 37128c35198d..2afea905f7f3 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -140,8 +140,8 @@ static const char * const imx8mn_enet_timer_sels[] =3D = {"osc_24m", "sys_pll2_100m" "clk_ext4", "video_pll_out", }; =20 static const char * const imx8mn_enet_phy_sels[] =3D {"osc_24m", "sys_pll2= _50m", "sys_pll2_125m", - "sys_pll2_200m", "sys_pll2_500m", "video_pll_out", - "audio_pll2_out", }; + "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mn_nand_sels[] =3D {"osc_24m", "sys_pll2_500= m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", --=20 2.32.0