From nobody Wed Apr 8 12:14:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A0D6C43219 for ; Thu, 17 Nov 2022 05:32:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234736AbiKQFcF (ORCPT ); Thu, 17 Nov 2022 00:32:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229658AbiKQFcC (ORCPT ); Thu, 17 Nov 2022 00:32:02 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34146554DC for ; Wed, 16 Nov 2022 21:32:01 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id l2so599178pld.13 for ; Wed, 16 Nov 2022 21:32:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J2RysX7TiVCclv2UJBtgXviDFq2/T3mQypqGPEA1b7s=; b=RZsVifCuuHh4V2cxHmbtLYLghbm1LoZSUWYte+QctCQW1n0hXcgdQfISnQVDiXRd4d OTtW281b+r7/C8nkpSesqja0z3EkWcRrWujsthf3dQi+PL0wKCsll/S6gT1HTE/Ahv7S oPiU38AWsO9mG3YspF5IePBxZC1cK5bZgd6AfXtA73gvXJIzgWObGX5qmMXcwpabYqaD LJGiwb6dWfP5sXX8ac/rSCQZkzMyxASwAcH/xZP/DzMz68duHb2on/psSLpqbNum4a5w GYr1M8pfADMvBsAgDy7UFaPE/cn49s05qL91v6tXGr+kzJBMn5mEAJqFRQWYVOgLbDvc 9XdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J2RysX7TiVCclv2UJBtgXviDFq2/T3mQypqGPEA1b7s=; b=2p//P4shsZm5AZaEYXWasd+jJmC5+dKH3Q23ZgfIUr5kOs8twsNBBRwPFVjkQu4Rd6 IWiF59brcyEbZeeWdNpTjFOpFN7F06nFLIfQ1vtrxC2Z09w210/k74jS87/07qxvReRe YNEC0VmLJwcq3QBTrlOcLFPwrg47yh3Mf0p9LkZAd0gmp45uxt3C3KqBe6HFsK7kl+bF ELtRDoXCNklPSOePJzBAO+HWQ7tATaRTUOv73n4CoH7s8MxXAjUAee1m+9ne0PFMp3sr 8bBbm8RuGYX3nj5Z0QZ0qkdZTEQtzOS/50tkOJHgnqI9dD/JwI0ndLwvKlSRbGEYwN6H 3hxw== X-Gm-Message-State: ANoB5plpJ6sNmBA0xiCpG0EXXfQw3UXcjKLJ16Zg0ykSdeSosZXAzqiU 6kVngrZ+UtIi6ZV1ahEU3S2H X-Google-Smtp-Source: AA0mqf6KxByoSdNPUxxW77iz8DQDSNjXZ3URm4SVhOb0yWJnDsmL1LIGuoSI/jJxNa1Wmy5cAJoPPg== X-Received: by 2002:a17:902:d38c:b0:186:8c19:d436 with SMTP id e12-20020a170902d38c00b001868c19d436mr1245857pld.96.1668663120669; Wed, 16 Nov 2022 21:32:00 -0800 (PST) Received: from localhost.localdomain ([117.193.208.31]) by smtp.gmail.com with ESMTPSA id q4-20020a17090311c400b001865c298588sm96600plh.258.2022.11.16.21.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 21:31:59 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v7 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider Date: Thu, 17 Nov 2022 11:01:42 +0530 Message-Id: <20221117053145.10409-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117053145.10409-1-manivannan.sadhasivam@linaro.org> References: <20221117053145.10409-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e58c55f78aaa..676d369a6fdd 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -56,6 +56,9 @@ properties: '#freq-domain-cells': const: 1 =20 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -83,6 +86,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; cache-unified; @@ -103,6 +107,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; cache-unified; @@ -118,6 +123,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; cache-unified; @@ -133,6 +139,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; cache-unified; @@ -148,6 +155,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; cache-unified; @@ -163,6 +171,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; cache-unified; @@ -178,6 +187,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; cache-unified; @@ -193,6 +203,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_700: l2-cache { compatible =3D "cache"; cache-unified; @@ -215,6 +226,7 @@ examples: clock-names =3D "xo", "alternate"; =20 #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; }; }; ... --=20 2.25.1