From nobody Wed Apr 8 10:18:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A0D6C43219 for ; Thu, 17 Nov 2022 05:32:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234736AbiKQFcF (ORCPT ); Thu, 17 Nov 2022 00:32:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229658AbiKQFcC (ORCPT ); Thu, 17 Nov 2022 00:32:02 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34146554DC for ; Wed, 16 Nov 2022 21:32:01 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id l2so599178pld.13 for ; Wed, 16 Nov 2022 21:32:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J2RysX7TiVCclv2UJBtgXviDFq2/T3mQypqGPEA1b7s=; b=RZsVifCuuHh4V2cxHmbtLYLghbm1LoZSUWYte+QctCQW1n0hXcgdQfISnQVDiXRd4d OTtW281b+r7/C8nkpSesqja0z3EkWcRrWujsthf3dQi+PL0wKCsll/S6gT1HTE/Ahv7S oPiU38AWsO9mG3YspF5IePBxZC1cK5bZgd6AfXtA73gvXJIzgWObGX5qmMXcwpabYqaD LJGiwb6dWfP5sXX8ac/rSCQZkzMyxASwAcH/xZP/DzMz68duHb2on/psSLpqbNum4a5w GYr1M8pfADMvBsAgDy7UFaPE/cn49s05qL91v6tXGr+kzJBMn5mEAJqFRQWYVOgLbDvc 9XdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J2RysX7TiVCclv2UJBtgXviDFq2/T3mQypqGPEA1b7s=; b=2p//P4shsZm5AZaEYXWasd+jJmC5+dKH3Q23ZgfIUr5kOs8twsNBBRwPFVjkQu4Rd6 IWiF59brcyEbZeeWdNpTjFOpFN7F06nFLIfQ1vtrxC2Z09w210/k74jS87/07qxvReRe YNEC0VmLJwcq3QBTrlOcLFPwrg47yh3Mf0p9LkZAd0gmp45uxt3C3KqBe6HFsK7kl+bF ELtRDoXCNklPSOePJzBAO+HWQ7tATaRTUOv73n4CoH7s8MxXAjUAee1m+9ne0PFMp3sr 8bBbm8RuGYX3nj5Z0QZ0qkdZTEQtzOS/50tkOJHgnqI9dD/JwI0ndLwvKlSRbGEYwN6H 3hxw== X-Gm-Message-State: ANoB5plpJ6sNmBA0xiCpG0EXXfQw3UXcjKLJ16Zg0ykSdeSosZXAzqiU 6kVngrZ+UtIi6ZV1ahEU3S2H X-Google-Smtp-Source: AA0mqf6KxByoSdNPUxxW77iz8DQDSNjXZ3URm4SVhOb0yWJnDsmL1LIGuoSI/jJxNa1Wmy5cAJoPPg== X-Received: by 2002:a17:902:d38c:b0:186:8c19:d436 with SMTP id e12-20020a170902d38c00b001868c19d436mr1245857pld.96.1668663120669; Wed, 16 Nov 2022 21:32:00 -0800 (PST) Received: from localhost.localdomain ([117.193.208.31]) by smtp.gmail.com with ESMTPSA id q4-20020a17090311c400b001865c298588sm96600plh.258.2022.11.16.21.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 21:31:59 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v7 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider Date: Thu, 17 Nov 2022 11:01:42 +0530 Message-Id: <20221117053145.10409-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117053145.10409-1-manivannan.sadhasivam@linaro.org> References: <20221117053145.10409-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e58c55f78aaa..676d369a6fdd 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -56,6 +56,9 @@ properties: '#freq-domain-cells': const: 1 =20 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -83,6 +86,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; cache-unified; @@ -103,6 +107,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; cache-unified; @@ -118,6 +123,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; cache-unified; @@ -133,6 +139,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; cache-unified; @@ -148,6 +155,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; cache-unified; @@ -163,6 +171,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; cache-unified; @@ -178,6 +187,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; cache-unified; @@ -193,6 +203,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_700: l2-cache { compatible =3D "cache"; cache-unified; @@ -215,6 +226,7 @@ examples: clock-names =3D "xo", "alternate"; =20 #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; }; }; ... --=20 2.25.1 From nobody Wed Apr 8 10:18:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94CECC433FE for ; Thu, 17 Nov 2022 05:32:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238944AbiKQFcP (ORCPT ); Thu, 17 Nov 2022 00:32:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234503AbiKQFcL (ORCPT ); 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Wed, 16 Nov 2022 21:32:04 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v7 2/4] arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs Date: Thu, 17 Nov 2022 11:01:43 +0530 Message-Id: <20221117053145.10409-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117053145.10409-1-manivannan.sadhasivam@linaro.org> References: <20221117053145.10409-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index d32f08df743d..234d2722a4fa 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -51,6 +51,7 @@ CPU0: cpu@0 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -70,6 +71,7 @@ CPU1: cpu@100 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -86,6 +88,7 @@ CPU2: cpu@200 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -102,6 +105,7 @@ CPU3: cpu@300 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -118,6 +122,7 @@ CPU4: cpu@400 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -134,6 +139,7 @@ CPU5: cpu@500 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -151,6 +157,7 @@ CPU6: cpu@600 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -167,6 +174,7 @@ CPU7: cpu@700 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; 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charset="utf-8" Qcom CPUFreq hardware (EPSS/OSM) controls clock and voltage to the CPU cores. But this relationship is not represented with the clk framework so far. So, let's make the qcom-cpufreq-hw driver a clock provider. This makes the clock producer/consumer relationship cleaner and is also useful for CPU related frameworks like OPP to know the frequency at which the CPUs are running. The clock frequency provided by the driver is for each frequency domain. We cannot get the frequency of each CPU core because, not all platforms support per-core DCVS feature. Also the frequency supplied by the driver is the actual frequency that comes out of the EPSS/OSM block after the DCVS operation. This frequency is not same as what the CPUFreq framework has set but it is the one that gets supplied to the CPUs after throttling by LMh. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 45 +++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index 5e0598730a04..1faa325d3e52 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -54,6 +55,7 @@ struct qcom_cpufreq_data { bool cancel_throttle; struct delayed_work throttle_work; struct cpufreq_policy *policy; + struct clk_hw cpu_clk; =20 bool per_core_dcvs; =20 @@ -615,8 +617,20 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = =3D { .ready =3D qcom_cpufreq_ready, }; =20 +static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsign= ed long parent_rate) +{ + struct qcom_cpufreq_data *data =3D container_of(hw, struct qcom_cpufreq_d= ata, cpu_clk); + + return qcom_lmh_get_throttle_freq(data); +} + +static const struct clk_ops qcom_cpufreq_hw_clk_ops =3D { + .recalc_rate =3D qcom_cpufreq_hw_recalc_rate, +}; + static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct clk_hw_onecell_data *clk_data; struct device *dev =3D &pdev->dev; struct device *cpu_dev; struct clk *clk; @@ -659,8 +673,15 @@ static int qcom_cpufreq_hw_driver_probe(struct platfor= m_device *pdev) =20 qcom_cpufreq.soc_data =3D of_device_get_match_data(dev); =20 + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, num_domains), G= FP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num =3D num_domains; + for (i =3D 0; i < num_domains; i++) { struct qcom_cpufreq_data *data =3D &qcom_cpufreq.data[i]; + struct clk_init_data clk_init =3D {}; struct resource *res; void __iomem *base; =20 @@ -672,6 +693,30 @@ static int qcom_cpufreq_hw_driver_probe(struct platfor= m_device *pdev) =20 data->base =3D base; data->res =3D res; + + /* Register CPU clock for each frequency domain */ + clk_init.name =3D kasprintf(GFP_KERNEL, "qcom_cpufreq%d", i); + if (!clk_init.name) + return -ENOMEM; + + clk_init.flags =3D CLK_GET_RATE_NOCACHE; + clk_init.ops =3D &qcom_cpufreq_hw_clk_ops; + data->cpu_clk.init =3D &clk_init; + + ret =3D devm_clk_hw_register(dev, &data->cpu_clk); + if (ret < 0) { + dev_err(dev, "Failed to register clock %d: %d\n", i, ret); + return ret; + } + + clk_data->hws[i] =3D &data->cpu_clk; + kfree(clk_init.name); + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret < 0) { + dev_err(dev, "Failed to add clock provider\n"); + return ret; } =20 ret =3D cpufreq_register_driver(&cpufreq_qcom_hw_driver); --=20 2.25.1 From nobody Wed Apr 8 10:18:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A4E7C4332F for ; Thu, 17 Nov 2022 05:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239057AbiKQFcm (ORCPT ); Thu, 17 Nov 2022 00:32:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239145AbiKQFcR (ORCPT ); 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Wed, 16 Nov 2022 21:32:13 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam , stable@vger.kernel.org, Sudeep Holla Subject: [PATCH v7 4/4] cpufreq: qcom-hw: Fix the frequency returned by cpufreq_driver->get() Date: Thu, 17 Nov 2022 11:01:45 +0530 Message-Id: <20221117053145.10409-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117053145.10409-1-manivannan.sadhasivam@linaro.org> References: <20221117053145.10409-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The cpufreq_driver->get() callback is supposed to return the current frequency of the CPU and not the one requested by the CPUFreq core. Fix it by returning the frequency that gets supplied to the CPU after the DCVS operation of EPSS/OSM. Cc: stable@vger.kernel.org # v5.15 Fixes: 2849dd8bc72b ("cpufreq: qcom-hw: Add support for QCOM cpufreq HW dri= ver") Reported-by: Sudeep Holla Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 42 +++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index 1faa325d3e52..62f36c76e26c 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -131,7 +131,35 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq= _policy *policy, return 0; } =20 +static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *= data) +{ + unsigned int lval; + + if (qcom_cpufreq.soc_data->reg_current_vote) + lval =3D readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_v= ote) & 0x3ff; + else + lval =3D readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_st= ate) & 0xff; + + return lval * xo_rate; +} + +/* Get the current frequency of the CPU (after throttling) */ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) +{ + struct qcom_cpufreq_data *data; + struct cpufreq_policy *policy; + + policy =3D cpufreq_cpu_get_raw(cpu); + if (!policy) + return 0; + + data =3D policy->driver_data; + + return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ; +} + +/* Get the frequency requested by the cpufreq core for the CPU */ +static unsigned int qcom_cpufreq_get_freq(unsigned int cpu) { struct qcom_cpufreq_data *data; const struct qcom_cpufreq_soc_data *soc_data; @@ -292,18 +320,6 @@ static void qcom_get_related_cpus(int index, struct cp= umask *m) } } =20 -static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *= data) -{ - unsigned int lval; - - if (qcom_cpufreq.soc_data->reg_current_vote) - lval =3D readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_v= ote) & 0x3ff; - else - lval =3D readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_st= ate) & 0xff; - - return lval * xo_rate; -} - static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data) { struct cpufreq_policy *policy =3D data->policy; @@ -347,7 +363,7 @@ static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_da= ta *data) * If h/w throttled frequency is higher than what cpufreq has requested * for, then stop polling and switch back to interrupt mechanism. */ - if (throttled_freq >=3D qcom_cpufreq_hw_get(cpu)) + if (throttled_freq >=3D qcom_cpufreq_get_freq(cpu)) enable_irq(data->throttle_irq); else mod_delayed_work(system_highpri_wq, &data->throttle_work, --=20 2.25.1