From nobody Mon Apr 13 20:08:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9B54C433FE for ; Wed, 16 Nov 2022 14:34:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231778AbiKPOeP (ORCPT ); Wed, 16 Nov 2022 09:34:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233227AbiKPOeJ (ORCPT ); Wed, 16 Nov 2022 09:34:09 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 529A01022 for ; Wed, 16 Nov 2022 06:34:07 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id d13-20020a17090a3b0d00b00213519dfe4aso2549408pjc.2 for ; Wed, 16 Nov 2022 06:34:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J949pb6oSGDSDrDzQnofZv57QRZtSgdd5WM9tdGxJOI=; b=Ua4js2xUH13y9YJfd/++dnUqRrCU6gh/BGjac2YDHLyMdj7IDtLqkHguJsTLibtnlg aChLDMTm7RNnd6gbwD2Bq5uaWus+Jug4GepB2uQ1ShPcxwl4phrrvBwrCrXYgcQOpmbv G8aCwVLL3oftm4XYvIX8kCTUCM62cFh8rZx4L0io1e6+Of2gjtoqWo7DhECb4URfF70S pTSP0lUtzXm1gBBltvB9xxd9meXREtE1aDf/osfanimQLQwKKpcIGcodagCsfqIqyC2x qdKENKrFL1mg4PhhRrVuDzj/uA7cvUV8kExHF2apwos24ll3NR8V4LpcXSlPOjdO3HCN AMwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J949pb6oSGDSDrDzQnofZv57QRZtSgdd5WM9tdGxJOI=; b=UVBrzMqKyyD+izEKsCkN1XhOWqkEaRDmijSudfSS2cisvKiIV++R+VsKCT75jt6yFE Zamyq2DlrvxqsRqDa+nOhxD17+Es0qHoQc95PZKdSotAEv8WPe7pGlf3tMsKMuIy+zPa wPLXuPG/UhSB9MOnsD9cEHC3J/+PlT054Zh6Ho2uvJDlf260KIL0pO10pZQhdrF7eMXY V8gELUkM75S3nQKf637h1XkrS5Is4UeDtBnpM7ex96DQc5RCTt0qxd9w9R5AIDPPMO+Z aQSrIdmkjgsEZ3nkSHT9MDtGTwpKFox0xb+4IN1TqqskvdgixIulDu6N8dNGCaQadqxx rioQ== X-Gm-Message-State: ANoB5pml1YJQ9pFX/iqA2hB4H6LvQcLNszONk2eRWxueAP09hlDfdBjs DH+WXN7oECZHpWaJdlLL3cLOnPHwe9Fb X-Google-Smtp-Source: AA0mqf79RrSKuJIZq60BQ4CqKLQiv1uhu3K2zvp3aqmCiXZ+40m8zlanvmgfZnGCpIIR/YcaEjv82Q== X-Received: by 2002:a17:902:c412:b0:187:1380:4398 with SMTP id k18-20020a170902c41200b0018713804398mr9194888plk.134.1668609246905; Wed, 16 Nov 2022 06:34:06 -0800 (PST) Received: from localhost.localdomain ([59.92.100.153]) by smtp.gmail.com with ESMTPSA id e8-20020a63e008000000b0043c732e1536sm9560974pgh.45.2022.11.16.06.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 06:34:05 -0800 (PST) From: Manivannan Sadhasivam To: bjorn.andersson@linaro.org, bp@alien8.de, mchehab@kernel.org Cc: james.morse@arm.com, rric@kernel.org, linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, quic_saipraka@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 1/2] EDAC/qcom: Get rid of hardcoded register offsets Date: Wed, 16 Nov 2022 20:03:51 +0530 Message-Id: <20221116143352.289303-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221116143352.289303-1-manivannan.sadhasivam@linaro.org> References: <20221116143352.289303-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC EDAC register offsets varies between each SoC. Hardcoding the register offsets won't work and will often result in crash due to accessing the wrong locations. Hence, get the register offsets from the LLCC driver matching the individual SoCs. Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 116 ++++++++++++++--------------- include/linux/soc/qcom/llcc-qcom.h | 6 -- 2 files changed, 58 insertions(+), 64 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..04df70b7fea3 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -21,30 +21,9 @@ #define TRP_SYN_REG_CNT 6 #define DRP_SYN_REG_CNT 8 =20 -#define LLCC_COMMON_STATUS0 0x0003000c #define LLCC_LB_CNT_MASK GENMASK(31, 28) #define LLCC_LB_CNT_SHIFT 28 =20 -/* Single & double bit syndrome register offsets */ -#define TRP_ECC_SB_ERR_SYN0 0x0002304c -#define TRP_ECC_DB_ERR_SYN0 0x00020370 -#define DRP_ECC_SB_ERR_SYN0 0x0004204c -#define DRP_ECC_DB_ERR_SYN0 0x00042070 - -/* Error register offsets */ -#define TRP_ECC_ERROR_STATUS1 0x00020348 -#define TRP_ECC_ERROR_STATUS0 0x00020344 -#define DRP_ECC_ERROR_STATUS1 0x00042048 -#define DRP_ECC_ERROR_STATUS0 0x00042044 - -/* TRP, DRP interrupt register offsets */ -#define DRP_INTERRUPT_STATUS 0x00041000 -#define TRP_INTERRUPT_0_STATUS 0x00020480 -#define DRP_INTERRUPT_CLEAR 0x00041008 -#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 -#define TRP_INTERRUPT_0_CLEAR 0x00020484 -#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 - /* Mask and shift macros */ #define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) #define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16) @@ -60,15 +39,6 @@ #define DRP_TRP_INT_CLEAR GENMASK(1, 0) #define DRP_TRP_CNT_CLEAR GENMASK(1, 0) =20 -/* Config registers offsets*/ -#define DRP_ECC_ERROR_CFG 0x00040000 - -/* Tag RAM, Data RAM interrupt register offsets */ -#define CMN_INTERRUPT_0_ENABLE 0x0003001c -#define CMN_INTERRUPT_2_ENABLE 0x0003003c -#define TRP_INTERRUPT_0_ENABLE 0x00020488 -#define DRP_INTERRUPT_ENABLE 0x0004100c - #define SB_ERROR_THRESHOLD 0x1 #define SB_ERROR_THRESHOLD_SHIFT 24 #define SB_DB_TRP_INTERRUPT_ENABLE 0x3 @@ -86,9 +56,6 @@ enum { static const struct llcc_edac_reg_data edac_reg_data[] =3D { [LLCC_DRAM_CE] =3D { .name =3D "DRAM Single-bit", - .synd_reg =3D DRP_ECC_SB_ERR_SYN0, - .count_status_reg =3D DRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D DRP_ECC_ERROR_STATUS0, .reg_cnt =3D DRP_SYN_REG_CNT, .count_mask =3D ECC_SB_ERR_COUNT_MASK, .ways_mask =3D ECC_SB_ERR_WAYS_MASK, @@ -96,9 +63,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_DRAM_UE] =3D { .name =3D "DRAM Double-bit", - .synd_reg =3D DRP_ECC_DB_ERR_SYN0, - .count_status_reg =3D DRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D DRP_ECC_ERROR_STATUS0, .reg_cnt =3D DRP_SYN_REG_CNT, .count_mask =3D ECC_DB_ERR_COUNT_MASK, .ways_mask =3D ECC_DB_ERR_WAYS_MASK, @@ -106,9 +70,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_TRAM_CE] =3D { .name =3D "TRAM Single-bit", - .synd_reg =3D TRP_ECC_SB_ERR_SYN0, - .count_status_reg =3D TRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D TRP_ECC_ERROR_STATUS0, .reg_cnt =3D TRP_SYN_REG_CNT, .count_mask =3D ECC_SB_ERR_COUNT_MASK, .ways_mask =3D ECC_SB_ERR_WAYS_MASK, @@ -116,9 +77,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_TRAM_UE] =3D { .name =3D "TRAM Double-bit", - .synd_reg =3D TRP_ECC_DB_ERR_SYN0, - .count_status_reg =3D TRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D TRP_ECC_ERROR_STATUS0, .reg_cnt =3D TRP_SYN_REG_CNT, .count_mask =3D ECC_DB_ERR_COUNT_MASK, .ways_mask =3D ECC_DB_ERR_WAYS_MASK, @@ -126,7 +84,7 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, }; =20 -static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap) +static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *= llcc_bcast_regmap) { u32 sb_err_threshold; int ret; @@ -135,31 +93,31 @@ static int qcom_llcc_core_setup(struct regmap *llcc_bc= ast_regmap) * Configure interrupt enable registers such that Tag, Data RAM related * interrupts are propagated to interrupt controller for servicing */ - ret =3D regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_i= nterrupt_2_enable, TRP0_INTERRUPT_ENABLE, TRP0_INTERRUPT_ENABLE); if (ret) return ret; =20 - ret =3D regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->trp_i= nterrupt_0_enable, SB_DB_TRP_INTERRUPT_ENABLE, SB_DB_TRP_INTERRUPT_ENABLE); if (ret) return ret; =20 sb_err_threshold =3D (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT); - ret =3D regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG, + ret =3D regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_ecc_err= or_cfg, sb_err_threshold); if (ret) return ret; =20 - ret =3D regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_i= nterrupt_2_enable, DRP0_INTERRUPT_ENABLE, DRP0_INTERRUPT_ENABLE); if (ret) return ret; =20 - ret =3D regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE, + ret =3D regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_interru= pt_enable, SB_DB_DRP_INTERRUPT_ENABLE); return ret; } @@ -173,24 +131,28 @@ qcom_llcc_clear_error_status(int err_type, struct llc= c_drv_data *drv) switch (err_type) { case LLCC_DRAM_CE: case LLCC_DRAM_UE: - ret =3D regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, + drv->edac_reg_offset->drp_interrupt_clear, DRP_TRP_INT_CLEAR); if (ret) return ret; =20 - ret =3D regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, + drv->edac_reg_offset->drp_ecc_error_cntr_clear, DRP_TRP_CNT_CLEAR); if (ret) return ret; break; case LLCC_TRAM_CE: case LLCC_TRAM_UE: - ret =3D regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, + drv->edac_reg_offset->trp_interrupt_0_clear, DRP_TRP_INT_CLEAR); if (ret) return ret; =20 - ret =3D regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, + drv->edac_reg_offset->trp_ecc_error_cntr_clear, DRP_TRP_CNT_CLEAR); if (ret) return ret; @@ -203,16 +165,54 @@ qcom_llcc_clear_error_status(int err_type, struct llc= c_drv_data *drv) return ret; } =20 +struct qcom_llcc_syn_regs { + u32 synd_reg; + u32 count_status_reg; + u32 ways_status_reg; +}; + +static void get_reg_offsets(struct llcc_drv_data *drv, int err_type, + struct qcom_llcc_syn_regs *syn_regs) +{ + const struct llcc_edac_reg_offset *edac_reg_offset =3D drv->edac_reg_offs= et; + + switch (err_type) { + case LLCC_DRAM_CE: + syn_regs->synd_reg =3D edac_reg_offset->drp_ecc_sb_err_syn0; + syn_regs->count_status_reg =3D edac_reg_offset->drp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg_offset->drp_ecc_error_status0; + break; + case LLCC_DRAM_UE: + syn_regs->synd_reg =3D edac_reg_offset->drp_ecc_db_err_syn0; + syn_regs->count_status_reg =3D edac_reg_offset->drp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg_offset->drp_ecc_error_status0; + break; + case LLCC_TRAM_CE: + syn_regs->synd_reg =3D edac_reg_offset->trp_ecc_sb_err_syn0; + syn_regs->count_status_reg =3D edac_reg_offset->trp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg_offset->trp_ecc_error_status0; + break; + case LLCC_TRAM_UE: + syn_regs->synd_reg =3D edac_reg_offset->trp_ecc_db_err_syn0; + syn_regs->count_status_reg =3D edac_reg_offset->trp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg_offset->trp_ecc_error_status0; + break; + } +} + /* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/ static int dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) { struct llcc_edac_reg_data reg_data =3D edac_reg_data[err_type]; + struct qcom_llcc_syn_regs regs =3D { }; int err_cnt, err_ways, ret, i; u32 synd_reg, synd_val; =20 + get_reg_offsets(drv, err_type, ®s); + for (i =3D 0; i < reg_data.reg_cnt; i++) { - synd_reg =3D reg_data.synd_reg + (i * 4); + synd_reg =3D regs.synd_reg + (i * 4); ret =3D regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, &synd_val); if (ret) @@ -223,7 +223,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) } =20 ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + drv->offsets[bank] + regs.count_status_reg, &err_cnt); if (ret) goto clear; @@ -234,7 +234,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) reg_data.name, err_cnt); =20 ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + drv->offsets[bank] + regs.ways_status_reg, &err_ways); if (ret) goto clear; @@ -297,7 +297,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i =3D 0; i < drv->num_banks; i++) { ret =3D regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + drv->offsets[i] + drv->edac_reg_offset->drp_interrupt_status, &drp_error); =20 if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -313,7 +313,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) irq_rc =3D IRQ_HANDLED; =20 ret =3D regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + drv->offsets[i] + drv->edac_reg_offset->trp_interrupt_0_status, &trp_error); =20 if (!ret && (trp_error & SB_ECC_ERROR)) { @@ -340,7 +340,7 @@ static int qcom_llcc_edac_probe(struct platform_device = *pdev) int ecc_irq; int rc; =20 - rc =3D qcom_llcc_core_setup(llcc_driv_data->bcast_regmap); + rc =3D qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap); if (rc) return rc; =20 diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index bc2fb8343a94..d5b2d58e8857 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -57,9 +57,6 @@ struct llcc_slice_desc { /** * struct llcc_edac_reg_data - llcc edac registers data for each error type * @name: Name of the error - * @synd_reg: Syndrome register address - * @count_status_reg: Status register address to read the error count - * @ways_status_reg: Status register address to read the error ways * @reg_cnt: Number of registers * @count_mask: Mask value to get the error count * @ways_mask: Mask value to get the error ways @@ -68,9 +65,6 @@ struct llcc_slice_desc { */ struct llcc_edac_reg_data { char *name; - u64 synd_reg; - u64 count_status_reg; - u64 ways_status_reg; u32 reg_cnt; u32 count_mask; u32 ways_mask; --=20 2.25.1 From nobody Mon Apr 13 20:08:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 997B3C43217 for ; Wed, 16 Nov 2022 14:34:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233433AbiKPOeY (ORCPT ); Wed, 16 Nov 2022 09:34:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232915AbiKPOeN (ORCPT ); Wed, 16 Nov 2022 09:34:13 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F087CFE2 for ; Wed, 16 Nov 2022 06:34:11 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id v3-20020a17090ac90300b00218441ac0f6so3855766pjt.0 for ; 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Wed, 16 Nov 2022 06:34:11 -0800 (PST) Received: from localhost.localdomain ([59.92.100.153]) by smtp.gmail.com with ESMTPSA id e8-20020a63e008000000b0043c732e1536sm9560974pgh.45.2022.11.16.06.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 06:34:10 -0800 (PST) From: Manivannan Sadhasivam To: bjorn.andersson@linaro.org, bp@alien8.de, mchehab@kernel.org Cc: james.morse@arm.com, rric@kernel.org, linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, quic_saipraka@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 2/2] EDAC/qcom: Remove extra error no assignment in qcom_llcc_core_setup() Date: Wed, 16 Nov 2022 20:03:52 +0530 Message-Id: <20221116143352.289303-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221116143352.289303-1-manivannan.sadhasivam@linaro.org> References: <20221116143352.289303-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If the ret variable is initialized with -EINVAL, then there is no need to assign it again in the default case of qcom_llcc_core_setup(). Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 04df70b7fea3..0b6ca1f20b51 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -126,7 +126,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *d= rv, struct regmap *llcc_b static int qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv) { - int ret =3D 0; + int ret =3D -EINVAL; =20 switch (err_type) { case LLCC_DRAM_CE: @@ -158,7 +158,6 @@ qcom_llcc_clear_error_status(int err_type, struct llcc_= drv_data *drv) return ret; break; default: - ret =3D -EINVAL; edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n", err_type); } --=20 2.25.1