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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b002417e7f0685sm14576047wrb.9.2022.11.16.03.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 03:54:10 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: arm: rockchip: Add SOQuartz Blade Date: Wed, 16 Nov 2022 12:53:34 +0100 Message-Id: <20221116115337.541601-2-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> References: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds an enum for the SOQuartz Blade base board to the rockchip platforms binding. The SOQuartz Blade is a PoE-capable carrier board for the CM4 SoM form factor, designed around the SOQuartz CM4 System-on-Module. The board features the usual connectivity (GPIO, USB, HDMI, Ethernet) and an M.2 slot for SSDs. It may also be powered from a 5V barrel jack input, and has a 3.5mm jack for UART debug output. Signed-off-by: Nicolas Frattaroli Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index e40a3da90000..19797aca1fa0 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -578,6 +578,7 @@ properties: - description: Pine64 SoQuartz SoM items: - enum: + - pine64,soquartz-blade - pine64,soquartz-cm4io - const: pine64,soquartz - const: rockchip,rk3566 --=20 2.38.1 From nobody Mon Apr 13 13:26:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75274C433FE for ; Wed, 16 Nov 2022 12:02:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233449AbiKPMCq (ORCPT ); Wed, 16 Nov 2022 07:02:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233766AbiKPMBv (ORCPT ); Wed, 16 Nov 2022 07:01:51 -0500 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD6C6532DF; Wed, 16 Nov 2022 03:54:16 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id i186-20020a1c3bc3000000b003cfe29a5733so1420798wma.3; Wed, 16 Nov 2022 03:54:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UEGuDewmjyhmirLQjxFElQEIujVfJzvNkwrmuTJz5Vk=; b=XZAFWdidvtmaDU3OFfqNo6SEB1Luq9AC6uAyw9UIZtsr+nyn0DftR+YKTnsgcnGj/F LUwZzTxJzWzjxA+GEj3YthPaEeNSIt3qSGyNHC3fHQFE+ONaKzMTTXXMbUiHel/3rxVe qq3b2gcsaCJmsex6RfUbC4KglLaUGcY/eSNS0IQ8e0CChG0H8mOpE9TEHfrs+YPtt2XK TpS3cHcs7iz5qaJZkxEy+v3fjUegrihnfJGttt6qGlba8/PqbLxVfutS9uSkMxMs14YA XL85DTmrpGM4HQh+r2hw79GZahGSTrSZn1Ewe+bo1BIOT2GEPgn3HZ7nqU7SikdvrNMz i02A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UEGuDewmjyhmirLQjxFElQEIujVfJzvNkwrmuTJz5Vk=; b=kLlq82IIuQDo+8xyeBnUP89fWV1Vna0dQLLc+PSKlkXbwEtew0D00dYrVO9c2Qywcb Ph7WfRg/vChb6OWQZTquNoCapXGhpOsQ9gH9UNwduVHQMA5iNbZtJceVj+iWQWn/YGFb hTCNw7bxfzWrlbvb0Ls8BIrYxHG414I1u3mwN/qBXvHoyFdeuyAw1B33EwuoIxc5gonV lRV+5TNDgyVXbgv1QV+ZOxMIOHy87l4xfSXTe5apTQ99RcFYsHzxhwlVjfysVNEqF7wT a/GNIP0WQojbJG/Z0DJeb40ZEEqxFC/8YWoJ4eyecvIbWpkL6qKk/gf2m7h/DTIlbUET 8AwA== X-Gm-Message-State: ANoB5pmSVMCCtqdntBDFos5UQj/dGLcGbG2+pqWmr5MB3wwIcat3AQ4q LLSxx2vVuHwgtir8qjZxEEPzb1dJKoY= X-Google-Smtp-Source: AA0mqf6GuKoGpoc3LuHYFzWbgNV9xeQwdVmiIzEb5G2lT3W95pQdMreRs5QtP2mzRagzAA9d5Di97g== X-Received: by 2002:a05:600c:1e22:b0:3cf:a856:ba2f with SMTP id ay34-20020a05600c1e2200b003cfa856ba2fmr1978941wmb.37.1668599655296; Wed, 16 Nov 2022 03:54:15 -0800 (PST) Received: from localhost.localdomain (84-72-105-84.dclient.hispeed.ch. [84.72.105.84]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b002417e7f0685sm14576047wrb.9.2022.11.16.03.54.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 03:54:14 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Andrew Powers-Holmes , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] arm64: dts: rockchip: Add SOQuartz blade board Date: Wed, 16 Nov 2022 12:53:35 +0100 Message-Id: <20221116115337.541601-3-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> References: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Andrew Powers-Holmes This adds a device tree for the PINE64 SOQuartz blade baseboard, a 1U rack mountable baseboard for the CM4 form factor with PoE support designed for the SOQuartz CM4 System-on-Module. The board takes power from either PoE or a 5V DC input, and allows for mounting an M.2 SSD. The board also features one USB 2.0 host port, one HDMI output, a 3.5mm jack for UART, and the aforementioned gigabit networking port. Signed-off-by: Andrew Powers-Holmes [rebase, squash, reword, misc fixes] Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ 2 files changed, 195 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 832613143030..528a02b11552 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/= arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts new file mode 100644 index 000000000000..4e49bebf548b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include + +#include "rk3566-soquartz.dtsi" + +/ { + model =3D "PINE64 RK3566 SOQuartz on Blade carrier board"; + compatible =3D "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk35= 66"; + + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + /* labeled VCC_SSD in schematic */ + vcc3v3_pcie_p: vcc3v3-pcie-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vbus>; + }; + + vcc5v_dcin: vcc5v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; +}; + +&combphy2 { + phy-supply =3D <&vcc3v3_sys>; + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status =3D "okay"; + +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status =3D "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status =3D "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status =3D "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status =3D "disabled"; +}; + +&led_diy { + color =3D ; + function =3D LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger =3D "disk-activity"; + status =3D "okay"; +}; + +&led_work { + color =3D ; + function =3D LED_FUNCTION_STATUS; + linux,default-trigger =3D "heartbeat"; + status =3D "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply =3D <&vcc3v3_pcie_p>; + status =3D "okay"; +}; + +&rgmii_phy1 { + status =3D "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status =3D "disabled"; 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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b002417e7f0685sm14576047wrb.9.2022.11.16.03.54.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 03:54:19 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] dt-bindings: arm: rockchip: Add SOQuartz Model A Date: Wed, 16 Nov 2022 12:53:36 +0100 Message-Id: <20221116115337.541601-4-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> References: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SOQuartz Model A base board is a carrier board for the CM4 form factor, designed around the PINE64 SOQuartz CM4 SoM. The board sports "Model A" dimensions like the Quartz64 Model A, but is not to be confused with that. As for I/O, it features USB 2 ports, Gigabit Ethernet, a PCIe 2 x1 slot, HDMI, a 40-pin GPIO header, CSI/DSI connectors, an eDP flat-flex cable connector, a 12V DC barrel jack for power input and power/reset buttons as well as a microSD card slot. Signed-off-by: Nicolas Frattaroli Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 19797aca1fa0..1eff0afc19a1 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -580,6 +580,7 @@ properties: - enum: - pine64,soquartz-blade - pine64,soquartz-cm4io + - pine64,soquartz-model-a - const: pine64,soquartz - const: rockchip,rk3566 =20 --=20 2.38.1 From nobody Mon Apr 13 13:26:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44F05C433FE for ; Wed, 16 Nov 2022 12:02:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233103AbiKPMCl (ORCPT ); Wed, 16 Nov 2022 07:02:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233449AbiKPMBz (ORCPT ); Wed, 16 Nov 2022 07:01:55 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7110653ED3; Wed, 16 Nov 2022 03:54:25 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id t1so11724477wmi.4; Wed, 16 Nov 2022 03:54:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6/TfDkn8E1wKATyX/gU0RGSZ6sAmInYSFUBAN2pVLwE=; b=YD7wB7w/GkdzSuZ6qei1xiZ6SCDp0GrCM7QiCDDnECjuXQ0TndJIfsywTN7mftv5mq 9s9O8u8jdMpaY+wPKwQVKlHjfmtuXkjjN7AwXBqRYpCkU1xSk3g1vIaQ+VGFJqH80aWI KUDXvwKhVj+rBBS8ByVNjk69v/vBlxSFpxKcH+Jf4qR9wcEl0orO3KVpG5/7bpezn1sA 5JyR9CLORrmr85lxrmniEdCJJczzf8uFIAIHwfcbWRxypVUlk9vReXNu8vLHnmX6FpII 3rp/CV3z9SwUXCPiEl55or5OqC1aAcbXETdE9qpnYjyC4BBsF7GPKNCGwcE4KIdqOjVk 6i5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6/TfDkn8E1wKATyX/gU0RGSZ6sAmInYSFUBAN2pVLwE=; b=37+Z1isRAQA5H67Q1ONPUk9RB3t+kjV4IX3swL5r+7Vkq/12oJs9dNz5deYtpAURD0 s1JXTl2m4RUOcL65BVsISi4WhM/DB3c7kOsph0fKFR1/JjyO4lZL9RUQOJzfZFGeeGc7 gUxTzf7zB2TPTwHwGLSnA8G5vvrWNqDZwLjDVbWFNWhYHUYdyH+trecrJ0QKJwK8498n q/vFmHCz5cWj+Ist5tpSeLE9847GS0WLtuI8knduUSRKzd8XASOSIf5TrIRmDDyU2qIf DA3Oy3dT9g3yXHUfKS8Bxey8JncQz4BHFSk0M7ri3Oo2B1gSzsoRF1u8kKs1X8+AR+FB OrVQ== X-Gm-Message-State: ANoB5pkDGgMWxexEfR5SX7edE6Ye8J6nEOBbeWHo6eWINYr2f1r4mxAn xmhWJXPTKRf31QxHcK0wIEM= X-Google-Smtp-Source: AA0mqf4QWGFvPDsSzVAEknD3ZjQTMIx9AxZBaUsIpmWT0xh/vr0/hLw4QUYAgiF3kgrZztF9ZBQzSQ== X-Received: by 2002:a05:600c:34c6:b0:3cf:6f25:a713 with SMTP id d6-20020a05600c34c600b003cf6f25a713mr1860277wmq.184.1668599663991; Wed, 16 Nov 2022 03:54:23 -0800 (PST) Received: from localhost.localdomain (84-72-105-84.dclient.hispeed.ch. [84.72.105.84]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b002417e7f0685sm14576047wrb.9.2022.11.16.03.54.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 03:54:23 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Andrew Powers-Holmes , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] arm64: dts: rockchip: rk3566: Add SOQuartz Model A baseboard Date: Wed, 16 Nov 2022 12:53:37 +0100 Message-Id: <20221116115337.541601-5-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> References: <20221116115337.541601-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Andrew Powers-Holmes This patch adds the device tree for the "Model A" baseboard for the SOQuartz CM4 SoM, which is not to be confused with the Quartz64 Model A, which is the same form factor and SoC, but is not a CM4 carrier board. The board features a PCIe 2 x1 slot, USB 2 host ports, CSI/DSI connectors, an eDP FFC connector, gigabit ethernet, HDMI, and a 12V DC barrel jack. Also present is a microSD card slot, 40-pin GPIO, and a power and reset button. Signed-off-by: Andrew Powers-Holmes [rebase, misc fixes, reword] Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3566-soquartz-model-a.dts | 232 ++++++++++++++++++ 2 files changed, 233 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 528a02b11552..f78c0a935bce 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-model-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts b/arc= h/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts new file mode 100644 index 000000000000..2208dbfb7f0a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model =3D "PINE64 RK3566 SOQuartz on Model A carrier board"; + compatible =3D "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk= 3566"; + + /* labeled DCIN_12V in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + /* + * Labelled VCC3V0_SD in schematic to not conflict with PMIC + * regulator, it's 3.3v in actuality + */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc12v_pcie: vcc12v-pcie-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +/* phy for pcie */ +&combphy2 { + phy-supply =3D <&vcc3v3_sys>; + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status =3D "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible =3D "nxp,pcf85063"; + reg =3D <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status =3D "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status =3D "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status =3D "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status =3D "disabled"; +}; + +&led_diy { + status =3D "okay"; +}; + +&led_work { + status =3D "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply =3D <&vcc3v3_pcie>; + status =3D "okay"; +}; + +&rgmii_phy1 { + status =3D "okay"; +}; + +&rgmii_phy1 { + status =3D "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status =3D "disabled"; +}; + +/* + * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+ + * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys, + * so we use vcc3v3_sd here to ensure the regulator is enabled on older bo= ards. + */ +&sdmmc0 { + vmmc-supply =3D <&vcc3v3_sd>; + status =3D "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status =3D "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status =3D "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_usb>; + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&vbus { + vin-supply =3D <&vcc5v0_usb>; +}; + +&vcc3v3_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + status =3D "okay"; +}; --=20 2.38.1