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Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index c32bcded2aef..e3cdd8bccb0c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -1152,6 +1153,45 @@ IPCC_MPROC_SIGNAL_GLINK_QMP =20 label =3D "lpass"; qcom,remote-pid =3D <2>; + + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + qcom,intents =3D <512 20>; + + q6apm: q6apm { + reg =3D ; + compatible =3D "qcom,q6apm"; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", "msm/adsp/audio_pd"; + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; + #sound-dai-cells =3D <1>; + iommus =3D <&apps_smmu 0x0c01 0x0>; + }; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + }; + + q6prm: q6prm { + reg =3D ; + compatible =3D "qcom,q6prm"; + #clock-cells =3D <2>; + qcom,protection-domain =3D "avs/audio", "msm/adsp/audio_pd"; + q6prmcc: cc { + compatible =3D "qcom,q6prm-lpass-clocks"; + #clock-cells =3D <2>; + }; + }; + + }; + }; }; =20 --=20 2.25.1 From nobody Mon Apr 13 17:14:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 513EEC4332F for ; Tue, 15 Nov 2022 17:03:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231436AbiKORDi (ORCPT ); Tue, 15 Nov 2022 12:03:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231161AbiKORDL (ORCPT ); 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Tue, 15 Nov 2022 09:02:58 -0800 (PST) From: Srinivas Kandagatla To: agross@kernel.org, andersson@kernel.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 2/3] arm64: dts: qcom: sc8280xp/sa8540p: add SoundWire and LPASS Date: Tue, 15 Nov 2022 17:02:41 +0000 Message-Id: <20221115170242.150246-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221115170242.150246-1-srinivas.kandagatla@linaro.org> References: <20221115170242.150246-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add LPASS Codecs along with SoundWire controller for TX, RX, WSA and VA mac= ros along with LPASS LPI pinctrl node. Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 324 +++++++++++++++++++++++++ 1 file changed, 324 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index e3cdd8bccb0c..a87d58bee1e0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include =20 @@ -1115,6 +1116,9 @@ usb_2_ssphy1: phy@88f1e00 { }; }; =20 + sound: sound { + }; + remoteproc_adsp: remoteproc@3000000 { compatible =3D "qcom,sc8280xp-adsp-pas"; reg =3D <0 0x03000000 0 0x100>; @@ -1195,6 +1199,326 @@ q6prmcc: cc { }; }; =20 + rxmacro: rxmacro@3200000 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rx_swr_active>; + compatible =3D "qcom,sc8280xp-lpass-rx-macro"; + reg =3D <0 0x3200000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_N= O>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_AT= TRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_= NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + /* RX */ + swr1: soundwire-controller@3210000 { + reg =3D <0 0x3210000 0 0x2000>; + compatible =3D "qcom,soundwire-v1.6.0"; + interrupts =3D ; + clocks =3D <&rxmacro>; + clock-names =3D "iface"; + label =3D "RX"; + qcom,din-ports =3D <0>; + qcom,dout-ports =3D <5>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; + qcom,ports-hstop =3D /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + txmacro: txmacro@3220000 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tx_swr_active>; + compatible =3D "qcom,sc8280xp-lpass-tx-macro"; + reg =3D <0 0x3220000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRI= BUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO= >; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + clock-output-names =3D "mclk"; + #address-cells =3D <2>; + #size-cells =3D <2>; + #sound-dai-cells =3D <1>; + }; + + /* TX */ + swr2: soundwire-controller@3330000 { + reg =3D <0 0x3330000 0 0x2000>; + compatible =3D "qcom,soundwire-v1.6.0"; + interrupts-extended =3D <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "core", "wake"; + + clocks =3D <&vamacro>; + clock-names =3D "iface"; + label =3D "TX"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <0>; + qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x03 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x00 0x02 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstart =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstop =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-word-length =3D /bits/ 8 <0xFF 0x00 0xFF 0xFF>; + qcom,ports-block-group-count =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-lane-control =3D /bits/ 8 <0x00 0x01 0x00 0x00>; + qcom,port-offset =3D <1>; + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + wsamacro: codec@3240000 { + compatible =3D "qcom,sc8280xp-lpass-wsa-macro"; + reg =3D <0 0x03240000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_= COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_= NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_A= TTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPL= E_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wsa_swr_active>; + }; + + /* WSA */ + swr0: soundwire-controller@3250000 { + reg =3D <0 0x03250000 0 0x2000>; + compatible =3D "qcom,soundwire-v1.6.0"; + interrupts =3D ; + clocks =3D <&wsamacro>; + clock-names =3D "iface"; + + qcom,din-ports =3D <2>; + qcom,dout-ports =3D <6>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x= 0f 0x0f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x= 0a>; + qcom,ports-offset2 =3D /bits/ 8 <0xFF 0x00 0x1f 0xff 0x00 0x1f 0x00 0x= 00>; + qcom,ports-hstart =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F>; + qcom,ports-hstop =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF= >; + qcom,ports-word-length =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF= 0xFF>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 = 0xFF 0xFF>; + qcom,ports-block-group-count =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F 0xFF 0xFF>; + qcom,ports-lane-control =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F 0xFF>; + qcom,port-offset =3D <1>; + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + vamacro: codec@3370000 { + compatible =3D "qcom,sc8280xp-lpass-va-macro"; + reg =3D <0 0x03370000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + + clock-names =3D "mclk", "npl", "macro", "dcodec"; + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRI= BUTE_COUPLE_NO>; + assigned-clock-rates =3D <19200000>; + + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + lpass_tlmm: pinctrl@33c0000 { + compatible =3D "qcom,sc8280xp-lpass-lpi-pinctrl"; + reg =3D <0 0x33c0000 0x0 0x20000>, + <0 0x3550000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 18>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + wsa_swr_active: wsa-swr-active-pins { + clk { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + + }; + }; + + tx_swr_active: tx_swr-active-pins { + clk { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + pins =3D "gpio1", "gpio2"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx_swr-active-pins { + clk { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-pins { + clk { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_active: dmic01-active-pins { + clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic01_sleep: dmic01-sleep-pins { + clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <2>; + pull-down; + input-enable; + }; + }; + + dmic02_active: dmic02-active-pins { + clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic02_sleep: dmic02-sleep-pins { + clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <2>; + pull-down; + input-enable; + }; + }; + }; + usb_0_qmpphy: phy-wrapper@88ec000 { compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; reg =3D <0 0x088ec000 0 0x1e4>, --=20 2.25.1 From nobody Mon Apr 13 17:14:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D81EC433FE for ; Tue, 15 Nov 2022 17:03:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231359AbiKORDd (ORCPT ); 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Tue, 15 Nov 2022 09:03:01 -0800 (PST) From: Srinivas Kandagatla To: agross@kernel.org, andersson@kernel.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 3/3] arm64: dts: qcom: sc8280xp: Add soundcard support Date: Tue, 15 Nov 2022 17:02:42 +0000 Message-Id: <20221115170242.150246-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221115170242.150246-1-srinivas.kandagatla@linaro.org> References: <20221115170242.150246-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for SoundCard on X13s. This patch adds support for Headset Playback, record and 2 DMICs on the Panel along with the regulators required for powering up the LPASS codecs. Signed-off-by: Srinivas Kandagatla --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 213 ++++++++++++++++++ 1 file changed, 213 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index b2b744bb8a53..99c3021e8149 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -58,6 +58,16 @@ vreg_misc_3p3: regulator-misc-3p3 { regulator-boot-on; regulator-always-on; }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "VPH_VCC3R9"; + regulator-min-microvolt =3D <3900000>; + regulator-max-microvolt =3D <3900000>; + + regulator-always-on; + regulator-boot-on; + }; }; =20 &apps_rsc { @@ -67,6 +77,13 @@ pmc8280-1-rpmh-regulators { =20 vdd-l3-l5-supply =3D <&vreg_s11b>; =20 + vreg_s10b: smps10 { + regulator-name =3D "vreg_s10b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + vreg_s11b: smps11 { regulator-name =3D "vreg_s11b"; regulator-min-microvolt =3D <1272000>; @@ -74,6 +91,13 @@ vreg_s11b: smps11 { regulator-initial-mode =3D ; }; =20 + vreg_s12b: smps12 { + regulator-name =3D "vreg_s12b"; + regulator-min-microvolt =3D <984000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + vreg_l3b: ldo3 { regulator-name =3D "vreg_l3b"; regulator-min-microvolt =3D <1200000>; @@ -102,6 +126,7 @@ vreg_l6b: ldo6 { pmc8280c-rpmh-regulators { compatible =3D "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id =3D "c"; + vdd-bob-supply =3D <&vph_pwr>; =20 vreg_l1c: ldo1 { regulator-name =3D "vreg_l1c"; @@ -123,6 +148,13 @@ vreg_l13c: ldo13 { regulator-max-microvolt =3D <3072000>; regulator-initial-mode =3D ; }; + + vreg_bob: bob { + regulator-name =3D "vreg_bob"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; }; =20 pmc8280-2-rpmh-regulators { @@ -268,6 +300,80 @@ &remoteproc_nsp0 { status =3D "okay"; }; =20 +&sound { + compatible =3D "qcom,sc8280xp-sndcard"; + model =3D "SC8280XP-LENOVO-X13S"; + audio-routing =3D + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + codec { + sound-dai =3D <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai =3D <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; + }; + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wsa-dai-link { + link-name =3D "WSA Playback"; + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; + platform { + sound-dai =3D <&q6apm>; + }; + }; + + va-dai-link { + link-name =3D "VA Capture"; + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + + codec { + sound-dai =3D <&vamacro 0>; + }; + }; +}; + &usb_0 { status =3D "okay"; }; @@ -346,9 +452,96 @@ edp_bl_pwm: edp-bl-pwm-state { }; }; =20 +&soc { + wcd938x: codec { + compatible =3D "qcom,wcd9380-codec"; + #sound-dai-cells =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wcd_default>; + reset-gpios =3D <&tlmm 106 0>; + + vdd-buck-supply =3D <&vreg_s10b>; + vdd-rxtx-supply =3D <&vreg_s10b>; + vdd-io-supply =3D <&vreg_s10b>; + vdd-mic-bias-supply =3D <&vreg_bob>; + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 5= 00000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + }; +}; + +&swr0 { + left_spkr: wsa8830-left@0,1 { + compatible =3D "sdw10217020200"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spkr_1_sd_n_active>; + powerdown-gpios =3D <&tlmm 178 GPIO_ACTIVE_HIGH>; + reg =3D <0 1>; + #thermal-sensor-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + #sound-dai-cells =3D <0>; + vdd-supply =3D <&vreg_s10b>; + }; + + right_spkr: wsa8830-right@0,2{ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spkr_2_sd_n_active>; + powerdown-gpios =3D <&tlmm 179 GPIO_ACTIVE_HIGH>; + compatible =3D "sdw10217020200"; + reg =3D <0 2>; + #thermal-sensor-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + #sound-dai-cells =3D <0>; + vdd-supply =3D <&vreg_s10b>; + }; +}; + + +&swr1 { + status =3D "okay"; + + wcd_rx: wcd9380-rx@0,4 { + compatible =3D "sdw20217010d00"; + reg =3D <0 4>; + qcom,rx-port-mapping =3D <1 2 3 4 5 6>; + + }; +}; + +&swr2 { + status =3D "okay"; + + wcd_tx: wcd9380-tx@0,3 { + compatible =3D "sdw20217010d00"; + reg =3D <0 3>; + qcom,tx-port-mapping =3D <1 1 2 3>; + }; +}; + +&vamacro { + pinctrl-0 =3D <&dmic01_active>, <&dmic02_active>; + pinctrl-names =3D "default"; + vdd-micb-supply =3D <&vreg_s10b>; + qcom,dmic-sample-rate =3D <600000>; +}; + &tlmm { gpio-reserved-ranges =3D <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7= >; =20 + wcd_default: wcd-default-state { + reset { + pins =3D "gpio106"; + function =3D "gpio"; + bias-disable; + }; + }; + kybd_default: kybd-default-state { disable { pins =3D "gpio102"; @@ -383,6 +576,26 @@ qup2_i2c5_default: qup2-i2c5-default-state { drive-strength =3D <16>; }; =20 + spkr_1_sd_n_active: spkr_1_sd_n_active { + perst-n { + pins =3D "gpio178"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + perst-n { + pins =3D "gpio179"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + tpad_default: tpad-default-state { int-n { pins =3D "gpio182"; --=20 2.25.1