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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id bf16-20020a056512259000b004b1b0f12cb4sm2152786lfb.201.2022.11.15.03.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Nov 2022 03:00:56 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Srinivas Kandagatla , Krzysztof Kozlowski Subject: [PATCH v2 1/3] arm64: dts: qcom: sm8450: add GPR node Date: Tue, 15 Nov 2022 12:00:51 +0100 Message-Id: <20221115110053.110319-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221115110053.110319-1-krzysztof.kozlowski@linaro.org> References: <20221115110053.110319-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Srinivas Kandagatla Add Generic Packet Router (GPR) device node with ADSP services. Signed-off-by: Srinivas Kandagatla Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 46f9576f786f..4b0a1eee8bd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -2134,6 +2135,45 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label =3D "lpass"; qcom,remote-pid =3D <2>; =20 + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + qcom,intents =3D <512 20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + q6apm: service@1 { + reg =3D ; + compatible =3D "qcom,q6apm"; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; + iommus =3D <&apps_smmu 0x1801 0x0>; + }; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + }; + + q6prm: service@2 { + reg =3D ; + compatible =3D "qcom,q6prm"; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible =3D "qcom,q6prm-lpass-clocks"; + #clock-cells =3D <2>; + }; + }; + }; + fastrpc { compatible =3D "qcom,fastrpc"; qcom,glink-channels =3D "fastrpcglink-apps-dsp"; --=20 2.34.1 From nobody Mon Apr 13 17:20:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F01E7C433FE for ; Tue, 15 Nov 2022 11:02:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232276AbiKOLCo (ORCPT ); Tue, 15 Nov 2022 06:02:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232569AbiKOLBU (ORCPT ); Tue, 15 Nov 2022 06:01:20 -0500 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C380A2DDA for ; Tue, 15 Nov 2022 03:00:59 -0800 (PST) Received: by mail-lj1-x22b.google.com with SMTP id d20so16981280ljc.12 for ; Tue, 15 Nov 2022 03:00:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3rvI5NQc7R87B2e4shRvCJ2q3MGVVh7DO6BpMHu6nOw=; b=lgr7neqm9nuTsaSx6i6nj1vmk+T4lLE+yoB/5Bh+No4q9LF/RE4oT84Hb0Eh5nist/ 3RKJa/vtMH6X1JIVuCCwLGnAhsEaNB3BOe8AHmstWT1hgPqiwBwKrhzmnbvjQ9MXi33Y //WgcQvVmepAVmbxNaui5XxfM8kcaakvJ0ZhXc2hYqkrIW+ULn2/zz/h3R7ZDmJQ2ioJ BHgHapnJGAyf9N+zRf5bKDV/imCe08gjqoIAis+LFlMLr7rWeIxkenKinBA2fugYFKL5 yBNNUp3pVQHksu0axXxi15AwFWMB0e2i6lvHla9ijWM6i7E+NDwEAvjN/xPnbLNSPzfT nyHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3rvI5NQc7R87B2e4shRvCJ2q3MGVVh7DO6BpMHu6nOw=; b=nBeM1poJylUY+3vAAUcN0JBtQFUc7P/HCsCzTX5GPJpAtUz50fb8OVuK9Kg8L04qUl kcxXmS6STjA56LB5HGXSd4cejap7/rLKosH66hxzsnKCeze4QNuRPB4bXJaNIkhcKTd7 TNQHNqdaSQv1xh6yRZL9hwhxkdMBbspq9AEyV5zhTEVz26Z8cp2Xg3WZhuivTypQYGz9 BjkEoJzpA4i5WliJp1n/xhK3pt8IefL0Bis8+U8r8RVK5Pb/pXY0nBAZWbk08muWRIVD Pm7IZcsnU9keSgRnFJOho4uW6PLL+P7+QN1EebTEcMdX9ikJV3yCTephxK6TFlzoF/lP S4Ow== X-Gm-Message-State: ANoB5pnLb3tQ8TqvE90uJZb3XSOK/2zrSJPLcx9s8fpCntyLM2aCg8Hn pVJKpbwpFmzlY7/FwTdxNCCmCQ== X-Google-Smtp-Source: AA0mqf4rOtkiguBQKa73pxsReQFsJ9qhgFQJqz9Uub3D55ldNocQbeYLBin9jxEQlHWmbiqy+GKEmQ== X-Received: by 2002:a05:651c:1245:b0:26f:bd73:489b with SMTP id h5-20020a05651c124500b0026fbd73489bmr6052275ljh.478.1668510058106; Tue, 15 Nov 2022 03:00:58 -0800 (PST) Received: from krzk-bin.NAT.warszawa.vectranet.pl (088156142067.dynamic-2-waw-k-3-2-0.vectranet.pl. [88.156.142.67]) by smtp.gmail.com with ESMTPSA id bf16-20020a056512259000b004b1b0f12cb4sm2152786lfb.201.2022.11.15.03.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Nov 2022 03:00:57 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Srinivas Kandagatla , Krzysztof Kozlowski Subject: [PATCH v2 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS Date: Tue, 15 Nov 2022 12:00:52 +0100 Message-Id: <20221115110053.110319-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221115110053.110319-1-krzysztof.kozlowski@linaro.org> References: <20221115110053.110319-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Srinivas Kandagatla Add Soundwire controllers, Low Power Audio SubSystem (LPASS) devices and LPASS pin controller. Signed-off-by: Srinivas Kandagatla Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Whitespace cleanups. 2. Correct include - do not use deprecated one. --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 295 +++++++++++++++++++++++++++ 1 file changed, 295 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 4b0a1eee8bd9..e80a7d09646f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 / { @@ -2097,6 +2098,212 @@ compute-cb@3 { }; }; =20 + wsa2macro: codec@31e0000 { + compatible =3D "qcom,sm8450-lpass-wsa-macro"; + reg =3D <0 0x031e0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_= COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_A= TTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_CO= UPLE_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wsa2_swr_active>; + }; + + /* WSA2 */ + swr4: soundwire-controller@31f0000 { + reg =3D <0 0x031f0000 0 0x2000>; + compatible =3D "qcom,soundwire-v1.7.0"; + interrupts =3D ; + clocks =3D <&wsa2macro>; + clock-names =3D "iface"; + + qcom,din-ports =3D <2>; + qcom,dout-ports =3D <6>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x= 0f 0x0f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x= 0a>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x= 00>; + qcom,ports-hstart =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F>; + qcom,ports-hstop =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF= >; + qcom,ports-word-length =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF= 0xFF>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 = 0xFF 0xFF>; + qcom,ports-block-group-count =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F 0xFF 0xFF>; + qcom,ports-lane-control =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F 0xFF>; + + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + rxmacro: codec@3200000 { + compatible =3D "qcom,sm8450-lpass-rx-macro"; + reg =3D <0 0x3200000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_A= TTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rx_swr_active>; + }; + + swr1: soundwire-controller@3210000 { + reg =3D <0 0x3210000 0 0x2000>; + compatible =3D "qcom,soundwire-v1.7.0"; + interrupts =3D ; + clocks =3D <&rxmacro>; + clock-names =3D "iface"; + label =3D "RX"; + qcom,din-ports =3D <0>; + qcom,dout-ports =3D <5>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; + qcom,ports-hstop =3D /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + txmacro: codec@3220000 { + compatible =3D "qcom,sm8450-lpass-tx-macro"; + reg =3D <0 0x3220000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_AT= TRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tx_swr_active>; + }; + + wsamacro: codec@3240000 { + compatible =3D "qcom,sm8450-lpass-wsa-macro"; + reg =3D <0 0x03240000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_= COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_A= TTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_CO= UPLE_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wsa_swr_active>; + }; + + /* WSA */ + swr0: soundwire-controller@3250000 { + reg =3D <0 0x03250000 0 0x2000>; + compatible =3D "qcom,soundwire-v1.7.0"; + interrupts =3D ; + clocks =3D <&wsamacro>; + clock-names =3D "iface"; + + qcom,din-ports =3D <2>; + qcom,dout-ports =3D <6>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x= 0f 0x0f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x= 0a>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x= 00>; + qcom,ports-hstart =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F>; + qcom,ports-hstop =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF= >; + qcom,ports-word-length =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF= 0xFF>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 = 0xFF 0xFF>; + qcom,ports-block-group-count =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F 0xFF 0xFF>; + qcom,ports-lane-control =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xF= F 0xFF>; + qcom,port-offset =3D <1>; + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + swr2: soundwire-controller@33b0000 { + reg =3D <0 0x33b0000 0 0x2000>; + compatible =3D "qcom,soundwire-v1.7.0"; + interrupts-extended =3D <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "core", "wake"; + + clocks =3D <&vamacro>; + clock-names =3D "iface"; + label =3D "TX"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <0>; + qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstart =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstop =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-word-length =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-block-group-count =3D /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x02 0x00 0x00>; + qcom,port-offset =3D <1>; + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + vamacro: codec@33f0000 { + compatible =3D "qcom,sm8450-lpass-va-macro"; + reg =3D <0 0x033f0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>; + clock-names =3D "mclk", "macro", "dcodec", "npl"; + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRI= BUTE_COUPLE_NO>; + assigned-clock-rates =3D <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + remoteproc_adsp: remoteproc@30000000 { compatible =3D "qcom,sm8450-adsp-pas"; reg =3D <0 0x030000000 0 0x100>; @@ -3030,6 +3237,91 @@ qup_uart20_default: qup-uart20-default-state { =20 }; =20 + lpass_tlmm: pinctrl@3440000{ + compatible =3D "qcom,sm8450-lpass-lpi-pinctrl"; + reg =3D <0 0x3440000 0x0 0x20000>, + <0 0x34d0000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,sm8450-smmu-500", "arm,mmu-500"; reg =3D <0 0x15000000 0 0x100000>; @@ -3507,6 +3799,9 @@ lpass_ag_noc: interconnect@3c40000 { }; }; =20 + sound: sound { + }; + thermal-zones { aoss0-thermal { polling-delay-passive =3D <0>; --=20 2.34.1 From nobody Mon Apr 13 17:20:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7DEDC43217 for ; Tue, 15 Nov 2022 11:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229690AbiKOLCi (ORCPT ); Tue, 15 Nov 2022 06:02:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238039AbiKOLBU (ORCPT ); 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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id bf16-20020a056512259000b004b1b0f12cb4sm2152786lfb.201.2022.11.15.03.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Nov 2022 03:00:58 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Srinivas Kandagatla , Krzysztof Kozlowski Subject: [PATCH v2 3/3] arm64: dts: qcom: sm8450-hdk: add sound support Date: Tue, 15 Nov 2022 12:00:53 +0100 Message-Id: <20221115110053.110319-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221115110053.110319-1-krzysztof.kozlowski@linaro.org> References: <20221115110053.110319-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Srinivas Kandagatla Add sound support to SM8450 HDK board. Tested setup so far is only two speakers (working) and head-phones (only one channel working). Signed-off-by: Srinivas Kandagatla Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v1: 1. Sort. 2. Correct include - do not use deprecated one and drop q6asm.h (not used). --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 160 ++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8450-hdk.dts index 4d75f9db08c2..baff71c0c680 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -6,6 +6,7 @@ /dts-v1/; =20 #include +#include #include "sm8450.dtsi" =20 / { @@ -406,6 +407,147 @@ &sdhc_2 { status =3D "okay"; }; =20 +&soc { + wcd938x: codec { + compatible =3D "qcom,wcd9380-codec"; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 5= 00000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + reset-gpios =3D <&tlmm 43 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <1>; + + vdd-buck-supply =3D <&vreg_s10b_1p8>; + vdd-rxtx-supply =3D <&vreg_s10b_1p8>; + vdd-io-supply =3D <&vreg_s10b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob>; + }; +}; + +&sound { + compatible =3D "qcom,sm8450-sndcard"; + model =3D "SM8450-HDK"; + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4"; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wsa-dai-link { + link-name =3D "WSA Playback"; + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + va-dai-link { + link-name =3D "VA Capture"; + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; +}; + +&swr0 { + right_spkr: speaker@0,1{ + compatible =3D "sdw10217020200"; + reg =3D <0 1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spkr_1_sd_n_active>; + powerdown-gpios =3D <&tlmm 1 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + #thermal-sensor-cells =3D <0>; + vdd-supply =3D <&vreg_s10b_1p8>; + }; + + left_spkr: speaker@0,2{ + compatible =3D "sdw10217020200"; + reg =3D <0 2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spkr_2_sd_n_active>; + powerdown-gpios =3D <&tlmm 89 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + #thermal-sensor-cells =3D <0>; + vdd-supply =3D <&vreg_s10b_1p8>; + }; +}; + +&swr1 { + status =3D "okay"; + + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010d00"; + reg =3D <0 4>; + qcom,rx-port-mapping =3D <1 2 3 4 5>; + }; +}; + +&swr2 { + status =3D "okay"; + + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010d00"; + reg =3D <0 3>; + /* ports: adc1_2, adc3_4, dmic0_3_mbhc, dmic4_7 */ + qcom,tx-port-mapping =3D <1 1 2 3>; + }; +}; + &tlmm { gpio-reserved-ranges =3D <28 4>, <36 4>; =20 @@ -461,3 +603,21 @@ &usb_1_qmpphy { vdda-phy-supply =3D <&vreg_l6b_1p2>; vdda-pll-supply =3D <&vreg_l1b_0p91>; }; + +&tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins =3D "gpio1"; + function =3D "gpio"; + drive-strength =3D <4>; + bias-disable; + output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins =3D "gpio89"; + function =3D "gpio"; + drive-strength =3D <4>; + bias-disable; + output-low; + }; +}; --=20 2.34.1