From nobody Mon Apr 13 21:42:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D193C433FE for ; Wed, 16 Nov 2022 10:55:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230031AbiKPKzC (ORCPT ); Wed, 16 Nov 2022 05:55:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238551AbiKPKy3 (ORCPT ); Wed, 16 Nov 2022 05:54:29 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EDFD10CA for ; Wed, 16 Nov 2022 02:43:15 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id d9so24499619wrm.13 for ; Wed, 16 Nov 2022 02:43:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=m40PHT4RBpEOlNADO2svZwYwf1RoA3KeZxV27wMJ4hA=; b=rtmesuYyxGZpieb/0skXjJUKwQmY3/kF+zXgdZMV8uyezTDmzg7Kb7U9OZwVJ0kSzt yBET3k5H03/kI+OAN0E+A0qjz/5q7gU0zwroh/Yx27ZOvnTRqfVb6hRfdwY4oSF/SRQf 3A1cBf9dGZApTHrA6C0d2o5a4tX8V1DHLSJF98K3NajkpR70ZiFBdN5LGJEczadqibaa U1q75m4pZnLD/ZjHLHgR4OyMLRZFdpYos/hW+w5Vn7ssTeJFE1EELt8rQmI1dUbNDhn2 s+Rfu9jBSHxICtEJbcv+nzSFf5SZZ8ziQsya8gLnGCz84yoBFufnICLkOtFxfzE3hXvC 4QLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m40PHT4RBpEOlNADO2svZwYwf1RoA3KeZxV27wMJ4hA=; b=HLCf2ob6uk/MaR3oAMUny/ZmmDhGkqiTsT4emPaK7T5uxw/HljjYs8MJQ0HpJkLo9M XKl1S334SXA6Vlir4hsT8zhZwehh7m92cy3NvoqnrdlGayHnxWbXfhyxRghYfo3Uhqqv xYuTC219eFqaRZO57SaB4P8ZitzpRLvlXg0mgUQh5XzEMqCtGr1Je5jYRmdl2D684Vte M5yNoFBCCJs0F0zuj06qzdWqQvYt/ZusRkmpByGBiyQkbHPcIa3KTMTP8CkU6XrDf5ZC rrjIvUO2Wmix2rF4ZhpbAsV5CGqkrlJhjuUB9Ai3FpyD9F2cSrifBjKvmdHvE0SrY3Nr oMpA== X-Gm-Message-State: ANoB5plKAjvrnSmayX1pw8lCDw4ypfudHeKmz+D/vJPiVphUqZUehhN0 he8X2Crq+dIyKsMh67JPwHN43g== X-Google-Smtp-Source: AA0mqf7cfLECW4ZhNd0/mL440gQseKdKUCjYEJ5ixW+b/UjdfuOmMAT7z2EtbIi3srq4MdG/+Bjfzg== X-Received: by 2002:a5d:52c6:0:b0:236:754e:f8b4 with SMTP id r6-20020a5d52c6000000b00236754ef8b4mr13373776wrv.478.1668595394071; Wed, 16 Nov 2022 02:43:14 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id t8-20020adff048000000b002238ea5750csm18010846wro.72.2022.11.16.02.43.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 02:43:13 -0800 (PST) From: Neil Armstrong Date: Wed, 16 Nov 2022 11:43:11 +0100 Subject: [PATCH 2/3] arm64: dts: qcom: sm8550: add adsp, cdsp & mdss support nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221115-topic-sm8550-upstream-dts-remoteproc-v1-2-379eec11d841@linaro.org> References: <20221115-topic-sm8550-upstream-dts-remoteproc-v1-0-379eec11d841@linaro.org> In-Reply-To: <20221115-topic-sm8550-upstream-dts-remoteproc-v1-0-379eec11d841@linaro.org> To: Bjorn Andersson , Andy Gross , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, Abel Vesa , Neil Armstrong , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds support for the aDSP, cDSP and MPSS Subsystems found in the SM8550 SoC. The aDSP, cDSP and MPSS needs: - smp2p support nodes to get event back from the subsystems - remoteproc nodes with glink-edge subnodes providing all needed resources to start and run the subsystems In addition, the MPSS Subsystem needs a rmtfs_mem dedicated memory zone. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 337 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 337 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 9e00778bb600..cac3adc4504f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -543,6 +543,15 @@ adspslpi_mem: adspslpi-region@9ea00000 { =20 /* Linux kernel image is loaded at 0xa8000000 */ =20 + rmtfs_mem: rmtfs-region@d4a80000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0xd4a80000 0x0 0x280000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D <15>; + }; + mpss_dsm_mem: mpss-dsm-region@d4d00000 { compatible =3D "qcom,mpss-dsm-mem"; reg =3D <0x0 0xd4d00000 0x0 0x3300000>; @@ -635,6 +644,89 @@ hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000= { }; }; =20 + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <94>, <432>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name =3D "ipa"; + #qcom,smem-state-cells =3D <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name =3D "ipa"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + soc: soc@0 { #address-cells =3D <2>; #size-cells =3D <2>; @@ -1388,6 +1480,48 @@ tcsr: clock-controller@1fc0000 { #reset-cells =3D <1>; }; =20 + remoteproc_mpss: remoteproc@4080000 { + compatible =3D "qcom,sm8550-mpss-pas"; + reg =3D <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended =3D <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SM8550_CX>, + <&rpmhpd SM8550_MSS>; + power-domain-names =3D "cx", "mss"; + + interconnects =3D <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region =3D <&mpss_mem &q6_mpss_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_modem_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label =3D "mpss"; + qcom,remote-pid =3D <1>; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible =3D "qcom,sm8550-lpass-lpiaon-noc"; reg =3D <0x0 0x07400000 0x0 0x19080>; @@ -2865,12 +2999,215 @@ system-cache-controller@25000000 { interrupts =3D ; }; =20 + remoteproc_adsp: remoteproc@30000000 { + compatible =3D "qcom,sm8550-adsp-pas"; + reg =3D <0x0 0x30000000 0x0 0x100>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SM8550_LCX>, + <&rpmhpd SM8550_LMX>; + power-domain-names =3D "lcx", "lmx"; + + interconnects =3D <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_= EBI1 0>; + + memory-region =3D <&adspslpi_mem &q6_adsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "lpass"; + qcom,remote-pid =3D <2>; + + fastrpc { + compatible =3D "qcom,fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "adsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x0>; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x0>; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x0>; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x0>; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu 0x1007 0x80>, + <&apps_smmu 0x1067 0x0>; + }; + }; + }; + }; + nsp_noc: interconnect@320c0000 { compatible =3D "qcom,sm8550-nsp-noc"; reg =3D <0x0 0x320C0000 0x0 0xE080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible =3D "qcom,sm8550-cdsp-pas"; + reg =3D <0x0 0x32300000 0x0 0x1400000>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SM8550_CX>, + <&rpmhpd SM8550_MXC>, + <&rpmhpd SM8550_NSP>; + power-domain-names =3D "cx", "mxc", "nsp"; + + interconnects =3D <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region =3D <&cdsp_mem &q6_cdsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "cdsp"; + qcom,remote-pid =3D <5>; + + fastrpc { + compatible =3D "qcom,fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x0c01 0x20>, + <&apps_smmu 0x19c1 0x10>; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x19c2 0x10>; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c03 0x20>, + <&apps_smmu 0x19c3 0x10>; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x19c4 0x10>; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x19c5 0x10>; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x19c6 0x10>; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c07 0x20>, + <&apps_smmu 0x19c7 0x10>; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x19c8 0x10>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; }; =20 thermal-zones { --=20 b4 0.10.1