From nobody Fri Sep 19 04:08:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99B1AC47088 for ; Tue, 29 Nov 2022 14:47:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235831AbiK2Or0 (ORCPT ); Tue, 29 Nov 2022 09:47:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235785AbiK2OrJ (ORCPT ); Tue, 29 Nov 2022 09:47:09 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 899495BD4C for ; Tue, 29 Nov 2022 06:47:07 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id m19so1936086wms.5 for ; Tue, 29 Nov 2022 06:47:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7Y6JWzzFOsrLeYSsZTyrPv8RLHe0kfmzZcIB/TwxDDY=; b=eAsQnM94KJ79HWoIAreMPRGqA9dOjKyQx8pyf+51+eil8i43dJ3/S8S/S8NOVKV8Rk 08Zw7b8yUwJ3hNxlqKXPMU61K1SLVC8pbDwmfihtATbmfPfvDJ+I5BFa0myWsBcNndd6 pYBXuaNQF1N1Xz9RzRXFJmTSDvglgaB3OiQCjc4hIMx26OjnQHKr18/yy/N/zW0PA2Ix 4sJlRarqKhvJ2UVFW56CpimYZATTL46NBcPI9C12d/FEK00AH2kpsh/O6sKADbC95UGH 3Uj2vMebzQIJLY6bxrHebUBli5lXyt0gMBhWfjagtxKMqJHUnJLhVMZiYWr5wcmStk9N DuWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7Y6JWzzFOsrLeYSsZTyrPv8RLHe0kfmzZcIB/TwxDDY=; b=lq/XA5T2tHkgQ4pqJs5jwAbA++zf/WFEMlSmn/s20BESdWjt6RotaLe2I+9Rcj+EiF NWp49+SM6i7vel/VfkF58zphM97jiT6cmX7QcF2Vpn6hHxUJN0LCVYau7TavCnojja+J r6ziuRnVpuNhYy9S41hK78saleEaCA+gSHtoZ0r3USoukcRYSDjVUeFjUhW+MXIZt1QR uRza26t/f5Wd4Kj9SkFU5kkyT77YjWSN/qHSCoCjlNgj+MzraXIyZUFwgZOlaNKNAHKf Gk3DzJ4BY9MbtXrhv/XO908pxmtEBBl10grTmtrV+u3V/+KMTpx8BclgXXk28llx2eE8 uqLw== X-Gm-Message-State: ANoB5pkRXz9B5VXm8523TLoYvkPAPLNryOwsdXW+q/HtjArgqjo8gcVI vnCF3vYVJ+LgauDWx2nWjmzxIA== X-Google-Smtp-Source: AA0mqf7nQy2PdMiIw6iD/weOfSKulN/rAFkJMAOlhZuPJ0o71Zjh8EEe0qhEfQg66C0h1xT9tUBb8A== X-Received: by 2002:a05:600c:1d81:b0:3cf:6ab3:4a60 with SMTP id p1-20020a05600c1d8100b003cf6ab34a60mr30379693wms.32.1669733225898; Tue, 29 Nov 2022 06:47:05 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id b10-20020adfee8a000000b00241dec4ad16sm13717792wro.96.2022.11.29.06.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 06:47:05 -0800 (PST) From: Neil Armstrong Date: Tue, 29 Nov 2022 15:47:03 +0100 Subject: [PATCH v3 3/6] soc: qcom: geni-se: add desc struct to specify clocks from device match data MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-3-f6a20dc9996e@linaro.org> References: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> To: Bjorn Andersson , Rob Herring , Andy Gross , Krzysztof Kozlowski Cc: Krzysztof Kozlowski , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Prepare support for the I2C Master Hub variant by moving the required clocks list to a new desc struct then passing it through the compatible match data. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/qcom-geni-se.c | 69 ++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 55 insertions(+), 14 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index a0ceeede450f..9ddee9fd11ba 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -81,19 +81,31 @@ */ =20 #define MAX_CLK_PERF_LEVEL 32 -#define NUM_AHB_CLKS 2 +#define MAX_CLKS 2 =20 /** * struct geni_wrapper - Data structure to represent the QUP Wrapper Core * @dev: Device pointer of the QUP wrapper core * @base: Base address of this instance of QUP wrapper core - * @ahb_clks: Handle to the primary & secondary AHB clocks + * @clks: Handle to the primary & optional secondary AHB clocks + * @num_clks: Count of clocks * @to_core: Core ICC path */ struct geni_wrapper { struct device *dev; void __iomem *base; - struct clk_bulk_data ahb_clks[NUM_AHB_CLKS]; + struct clk_bulk_data clks[MAX_CLKS]; + unsigned int num_clks; +}; + +/** + * struct geni_se_desc - Data structure to represent the QUP Wrapper resou= rces + * @clks: Name of the primary & optional secondary AHB clocks + * @num_clks: Count of clock names + */ +struct geni_se_desc { + unsigned int num_clks; + const char * const *clks; }; =20 static const char * const icc_path_names[] =3D {"qup-core", "qup-config", @@ -496,8 +508,7 @@ static void geni_se_clks_off(struct geni_se *se) struct geni_wrapper *wrapper =3D se->wrapper; =20 clk_disable_unprepare(se->clk); - clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), - wrapper->ahb_clks); + clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); } =20 /** @@ -528,15 +539,13 @@ static int geni_se_clks_on(struct geni_se *se) int ret; struct geni_wrapper *wrapper =3D se->wrapper; =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), - wrapper->ahb_clks); + ret =3D clk_bulk_prepare_enable(wrapper->num_clks, wrapper->clks); if (ret) return ret; =20 ret =3D clk_prepare_enable(se->clk); if (ret) - clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), - wrapper->ahb_clks); + clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); return ret; } =20 @@ -887,11 +896,33 @@ static int geni_se_probe(struct platform_device *pdev) return PTR_ERR(wrapper->base); =20 if (!has_acpi_companion(&pdev->dev)) { - wrapper->ahb_clks[0].id =3D "m-ahb"; - wrapper->ahb_clks[1].id =3D "s-ahb"; - ret =3D devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); + const struct geni_se_desc *desc; + int i; + + desc =3D device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + wrapper->num_clks =3D min_t(unsigned int, desc->num_clks, MAX_CLKS); + + for (i =3D 0; i < wrapper->num_clks; ++i) + wrapper->clks[i].id =3D desc->clks[i]; + + ret =3D of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells= "); + if (ret < 0) { + dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); + return ret; + } + + if (ret < wrapper->num_clks) { + dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", + dev->of_node, wrapper->num_clks); + return -EINVAL; + } + + ret =3D devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); if (ret) { - dev_err(dev, "Err getting AHB clks %d\n", ret); + dev_err(dev, "Err getting clks %d\n", ret); return ret; } } @@ -901,8 +932,18 @@ static int geni_se_probe(struct platform_device *pdev) return devm_of_platform_populate(dev); } =20 +static const char * const qup_clks[] =3D { + "m-ahb", + "s-ahb", +}; + +static const struct geni_se_desc qup_desc =3D { + .clks =3D qup_clks, + .num_clks =3D ARRAY_SIZE(qup_clks), +}; + static const struct of_device_id geni_se_dt_match[] =3D { - { .compatible =3D "qcom,geni-se-qup", }, + { .compatible =3D "qcom,geni-se-qup", .data =3D &qup_desc }, {} }; MODULE_DEVICE_TABLE(of, geni_se_dt_match); --=20 b4 0.10.1