From nobody Fri Sep 19 02:32:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C628C4708A for ; Tue, 29 Nov 2022 14:47:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234286AbiK2OrQ (ORCPT ); Tue, 29 Nov 2022 09:47:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235691AbiK2OrI (ORCPT ); Tue, 29 Nov 2022 09:47:08 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF8E259859 for ; Tue, 29 Nov 2022 06:47:05 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id r66-20020a1c4445000000b003d05a3775d4so5057735wma.3 for ; Tue, 29 Nov 2022 06:47:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MFuTdix/yEFsrkLuW0V5I25CPqOO/yLI32L0tLkZw6k=; b=R4h2Qpg9sZkYrDXmMCfMGw+BmcxI74XNfHVOJHHbNDfyHc+p0dMu+MfNd7y1Iu/bx+ ZmIAvnuX88R6ZWhkEvgxzH8bxaUekssv/ZYjcxpgIMDEPXOjdGA/sGjb6JoC1GUZKI5J oaMki7bjXkT4CzvYVyCBbTDDEVTF1SXmi8VRUtYgfcsxOipACdIucqGrs8Z6+rMnYXjF GTdMVrFiEQKxq5QEuMr0SXOlyT2Tng1dqyRLZDkP+KP9qeoPXx3m85v/DiZ/ExAykktI KleweXEQCkmxGJjfxEJX9e3xZhj2PIYEb6/qic7V6ClD+1TJk0TtV4mRFy8OGdFwxEM/ v29w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MFuTdix/yEFsrkLuW0V5I25CPqOO/yLI32L0tLkZw6k=; b=gssf6Bc0DO+W2ELbWVKnUspbghiZPFQycZFTBa6xa4Ig/dnWCIcw8L3RS+0yQ1eY98 8Ud9tFmoRtsKXYO4bcD69qeAFkflrBo4BSnp70hzWFDzSNLc/rcACrSACUubD5hrZLfC UDrS74OvQs30Sr6NKGzWVHTmG/XlH3MhvycYitvcf4ZjTZazf1nqUfLtM6VSQvOaELo9 NYbUUvg6P4Cs94SOQfPwoE9+mJsSqdVZU3Sn+gdrXqs0S++uQQUqZgzc27xZAhmFh5Ga 8ZgeQkkmRq2DMWUovYQjQlC62ocGJIgwddeklRiTgQVl5RRI5AvZ/s4U/4ogwgFhotDk c+OA== X-Gm-Message-State: ANoB5pmIR6tu1kPpdfE28Rh5tKubnjJ/d2sfSEGCNUOoZlmO93cOw9U/ 7MEtK6MyLJeXXlum6hvPB7HGIg== X-Google-Smtp-Source: AA0mqf5N2V7+ZxHFRJ6mDjLUAPfzTIwHfQjdYaTmjUIV1tEpJOoW+TkTCIw9P6kUxnJvG7icuh8sSg== X-Received: by 2002:a05:600c:2296:b0:3cf:baa6:8ca5 with SMTP id 22-20020a05600c229600b003cfbaa68ca5mr27410117wmf.178.1669733224199; Tue, 29 Nov 2022 06:47:04 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id b10-20020adfee8a000000b00241dec4ad16sm13717792wro.96.2022.11.29.06.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 06:47:03 -0800 (PST) From: Neil Armstrong Date: Tue, 29 Nov 2022 15:47:01 +0100 Subject: [PATCH v3 1/6] dt-bindings: qcom: geni-se: document I2C Master Hub wrapper variant MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-1-f6a20dc9996e@linaro.org> References: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> To: Bjorn Andersson , Rob Herring , Andy Gross , Krzysztof Kozlowski Cc: Krzysztof Kozlowski , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Document the variant compatible, forbid UART and SPI sub-nodes, and remove requirement for the Master AHB clock and iommu property. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 44 ++++++++++++++++++= +--- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b= /Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 2bf5293fc995..ab4df0205285 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -21,20 +21,19 @@ properties: compatible: enum: - qcom,geni-se-qup + - qcom,geni-se-i2c-master-hub =20 reg: description: QUP wrapper common register address and length. maxItems: 1 =20 clock-names: - items: - - const: m-ahb - - const: s-ahb + minItems: 1 + maxItems: 2 =20 clocks: - items: - - description: Master AHB Clock - - description: Slave AHB Clock + minItems: 1 + maxItems: 2 =20 "#address-cells": const: 2 @@ -81,6 +80,39 @@ patternProperties: description: GENI Serial Engine based UART Controller. $ref: /schemas/serial/qcom,serial-geni-qcom.yaml# =20 +allOf: + - if: + properties: + compatible: + contains: + const: qcom,geni-se-i2c-master-hub + then: + properties: + clock-names: + items: + - const: s-ahb + + clocks: + items: + - description: Slave AHB Clock + + iommus: false + + patternProperties: + "spi@[0-9a-f]+$": false + "serial@[0-9a-f]+$": false + else: + properties: + clock-names: + items: + - const: m-ahb + - const: s-ahb + + clocks: + items: + - description: Master AHB Clock + - description: Slave AHB Clock + additionalProperties: false =20 examples: --=20 b4 0.10.1 From nobody Fri Sep 19 02:32:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80205C4708A for ; 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Tue, 29 Nov 2022 06:47:05 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id b10-20020adfee8a000000b00241dec4ad16sm13717792wro.96.2022.11.29.06.47.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 06:47:04 -0800 (PST) From: Neil Armstrong Date: Tue, 29 Nov 2022 15:47:02 +0100 Subject: [PATCH v3 2/6] dt-bindings: i2c: qcom-geni: document I2C Master Hub serial I2C engine MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-2-f6a20dc9996e@linaro.org> References: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> To: Bjorn Andersson , Rob Herring , Andy Gross , Krzysztof Kozlowski Cc: Krzysztof Kozlowski , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Document the I2C Serial Engine variant used within the I2C Master Hub Wrapper. This serial engine variant lacks DMA support, requires a core clock, and since DMA support is lacking the memory interconnect path isn't needed. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 64 ++++++++++++++++++= ---- 1 file changed, 54 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml = b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 0e7ed00562e2..f5f7dc8f325c 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -10,18 +10,19 @@ maintainers: - Andy Gross - Bjorn Andersson =20 -allOf: - - $ref: /schemas/i2c/i2c-controller.yaml# - properties: compatible: - const: qcom,geni-i2c + enum: + - qcom,geni-i2c + - qcom,geni-i2c-master-hub =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clock-names: - const: se + minItems: 1 + maxItems: 2 =20 clock-frequency: default: 100000 @@ -35,13 +36,12 @@ properties: - const: rx =20 interconnects: + minItems: 2 maxItems: 3 =20 interconnect-names: - items: - - const: qup-core - - const: qup-config - - const: qup-memory + minItems: 2 + maxItems: 3 =20 interrupts: maxItems: 1 @@ -71,6 +71,50 @@ required: - clock-names - reg =20 +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: qcom,geni-i2c-master-hub + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: se + - const: core + + dmas: false + dma-names: false + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + else: + properties: + clocks: + maxItems: 1 + + clock-names: + const: se + + interconnects: + minItems: 3 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + - const: qup-memory + unevaluatedProperties: false =20 examples: --=20 b4 0.10.1 From nobody Fri Sep 19 02:32:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99B1AC47088 for ; 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Tue, 29 Nov 2022 06:47:05 -0800 (PST) From: Neil Armstrong Date: Tue, 29 Nov 2022 15:47:03 +0100 Subject: [PATCH v3 3/6] soc: qcom: geni-se: add desc struct to specify clocks from device match data MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-3-f6a20dc9996e@linaro.org> References: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> To: Bjorn Andersson , Rob Herring , Andy Gross , Krzysztof Kozlowski Cc: Krzysztof Kozlowski , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Prepare support for the I2C Master Hub variant by moving the required clocks list to a new desc struct then passing it through the compatible match data. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/qcom-geni-se.c | 69 ++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 55 insertions(+), 14 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index a0ceeede450f..9ddee9fd11ba 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -81,19 +81,31 @@ */ =20 #define MAX_CLK_PERF_LEVEL 32 -#define NUM_AHB_CLKS 2 +#define MAX_CLKS 2 =20 /** * struct geni_wrapper - Data structure to represent the QUP Wrapper Core * @dev: Device pointer of the QUP wrapper core * @base: Base address of this instance of QUP wrapper core - * @ahb_clks: Handle to the primary & secondary AHB clocks + * @clks: Handle to the primary & optional secondary AHB clocks + * @num_clks: Count of clocks * @to_core: Core ICC path */ struct geni_wrapper { struct device *dev; void __iomem *base; - struct clk_bulk_data ahb_clks[NUM_AHB_CLKS]; + struct clk_bulk_data clks[MAX_CLKS]; + unsigned int num_clks; +}; + +/** + * struct geni_se_desc - Data structure to represent the QUP Wrapper resou= rces + * @clks: Name of the primary & optional secondary AHB clocks + * @num_clks: Count of clock names + */ +struct geni_se_desc { + unsigned int num_clks; + const char * const *clks; }; =20 static const char * const icc_path_names[] =3D {"qup-core", "qup-config", @@ -496,8 +508,7 @@ static void geni_se_clks_off(struct geni_se *se) struct geni_wrapper *wrapper =3D se->wrapper; =20 clk_disable_unprepare(se->clk); - clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), - wrapper->ahb_clks); + clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); } =20 /** @@ -528,15 +539,13 @@ static int geni_se_clks_on(struct geni_se *se) int ret; struct geni_wrapper *wrapper =3D se->wrapper; =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), - wrapper->ahb_clks); + ret =3D clk_bulk_prepare_enable(wrapper->num_clks, wrapper->clks); if (ret) return ret; =20 ret =3D clk_prepare_enable(se->clk); if (ret) - clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), - wrapper->ahb_clks); + clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); return ret; } =20 @@ -887,11 +896,33 @@ static int geni_se_probe(struct platform_device *pdev) return PTR_ERR(wrapper->base); =20 if (!has_acpi_companion(&pdev->dev)) { - wrapper->ahb_clks[0].id =3D "m-ahb"; - wrapper->ahb_clks[1].id =3D "s-ahb"; - ret =3D devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); + const struct geni_se_desc *desc; + int i; + + desc =3D device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + wrapper->num_clks =3D min_t(unsigned int, desc->num_clks, MAX_CLKS); + + for (i =3D 0; i < wrapper->num_clks; ++i) + wrapper->clks[i].id =3D desc->clks[i]; + + ret =3D of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells= "); + if (ret < 0) { + dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); + return ret; + } + + if (ret < wrapper->num_clks) { + dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", + dev->of_node, wrapper->num_clks); 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Tue, 29 Nov 2022 06:47:06 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id b10-20020adfee8a000000b00241dec4ad16sm13717792wro.96.2022.11.29.06.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 06:47:06 -0800 (PST) From: Neil Armstrong Date: Tue, 29 Nov 2022 15:47:04 +0100 Subject: [PATCH v3 4/6] soc: qcom: geni-se: add support for I2C Master Hub wrapper variant MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-4-f6a20dc9996e@linaro.org> References: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> To: Bjorn Andersson , Rob Herring , Andy Gross , Krzysztof Kozlowski Cc: Krzysztof Kozlowski , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Add the clock list for the I2C Master Hub variant to a new desc struct then pass it through the I2C Master Hub compatible match data. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/qcom-geni-se.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index 9ddee9fd11ba..f0475b93ca73 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -942,8 +942,18 @@ static const struct geni_se_desc qup_desc =3D { .num_clks =3D ARRAY_SIZE(qup_clks), }; =20 +static const char * const i2c_master_hub_clks[] =3D { + "s-ahb", +}; + +static const struct geni_se_desc i2c_master_hub_desc =3D { + .clks =3D i2c_master_hub_clks, + .num_clks =3D ARRAY_SIZE(i2c_master_hub_clks), +}; + static const struct of_device_id geni_se_dt_match[] =3D { { .compatible =3D "qcom,geni-se-qup", .data =3D &qup_desc }, + { .compatible =3D "qcom,geni-se-i2c-master-hub", .data =3D &i2c_master_hu= b_desc }, {} }; MODULE_DEVICE_TABLE(of, geni_se_dt_match); --=20 b4 0.10.1 From nobody Fri Sep 19 02:32:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D7C4C4321E for ; Tue, 29 Nov 2022 14:47:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235464AbiK2Ord (ORCPT ); Tue, 29 Nov 2022 09:47:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235798AbiK2OrL (ORCPT ); Tue, 29 Nov 2022 09:47:11 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0382E59167 for ; Tue, 29 Nov 2022 06:47:09 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id v124-20020a1cac82000000b003cf7a4ea2caso14512630wme.5 for ; Tue, 29 Nov 2022 06:47:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=r8Au/1u0YFc5wyAQ+jpg2qjjEheMb69WJesiWy0RQrA=; b=sqVV6mE5EDGMLCdQ0r2xOMxQYA/ZiB+py+Zu5HitjrgvKRSlD/3xogpgtlk9Fi7De2 MBruJUji9QX7cgkXHXg9So8hpIeosiveFPMLJMUa0gMlGfS1I49ad803GetMB8lzcoSM Er/O6qdjw9lI7kzs4B7kd5MyU8j8bcgvTzZHym5B1CDpo7Kra3u1NMk4ybOnAKWMpxmE 7g2vBpH1vX8GmKG5w5Fsed3Tp2mgZ9oSiIQ/P/h5o/RT7GSkolSX7TiLbOQl7JkXVH+A DlYGqNKc/Rbq8XXaMR8zz4YvicNjRlzmqS/MQboUBZ41TOAK6ZYV92GWFqpRJAALJmCM k+tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r8Au/1u0YFc5wyAQ+jpg2qjjEheMb69WJesiWy0RQrA=; b=rwu5cH5e10B1OAIBYvFEc4JbDIpNjzaFdK2NnyIjmt7vXYmn1TvbcA42HRMJ5smfiy r0acdrAHfIbvahV3vT2UX69+UXBF6r0Tl08+gyc3pdwNABLflPK/5tI4hQUMmr7ZlZT2 cQICUrjQqXx7MmNjt1YpMBAhKYF75nLcIpuG7idgjJMcTlecyB2UVD4DeOFw+MmuLjfS +TI5o4DMzV2c+l7w5cg3vqXNQKXovrESV6S1y/1Qsm4MeojMtAUR+ux4siHKpprhMcRS fGUaf3tLNJnUdGmU+sVb053T10gyheeH2Bh6KTyGdj4zSmp50gIWm4/5c4DhaDkuJrFD JiyQ== X-Gm-Message-State: ANoB5plxv/iqUEZJInmHTlR3i2nG318JC7dVeNIXIFknsz3g8yAXUZSD ewCfycEO58kviyeFT/n61bWz7w== X-Google-Smtp-Source: AA0mqf7s4DMmTBdo0+HD1SGfzOoK0yl8tS4opOjcQMyXT3Q9m6LbsxEH2hD7kcHPEEdWGlSwnuO6Zw== X-Received: by 2002:a05:600c:4e47:b0:3cf:5657:4717 with SMTP id e7-20020a05600c4e4700b003cf56574717mr45112311wmq.87.1669733227577; Tue, 29 Nov 2022 06:47:07 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id b10-20020adfee8a000000b00241dec4ad16sm13717792wro.96.2022.11.29.06.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 06:47:07 -0800 (PST) From: Neil Armstrong Date: Tue, 29 Nov 2022 15:47:05 +0100 Subject: [PATCH v3 5/6] i2c: qcom-geni: add desc struct to prepare support for I2C Master Hub variant MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-5-f6a20dc9996e@linaro.org> References: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> To: Bjorn Andersson , Rob Herring , Andy Gross , Krzysztof Kozlowski Cc: Krzysztof Kozlowski , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Those I2C serial engines variants have some requirements: - a separate "core" clock - doesn't support DMA, thus no memory interconnect path - fixed FIFO size not discoverable in the HW_PARAM_0 register Add a desc struct specifying all those requirements which will be used in a next change when adding the I2C Master Hub serial engine compatible. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/i2c/busses/i2c-qcom-geni.c | 50 ++++++++++++++++++++++++++++++++++= +--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 84a77512614d..75dd0718c5a1 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -88,6 +88,7 @@ struct geni_i2c_dev { int cur_wr; int cur_rd; spinlock_t lock; + struct clk *core_clk; u32 clk_freq_out; const struct geni_i2c_clk_fld *clk_fld; int suspended; @@ -100,6 +101,13 @@ struct geni_i2c_dev { bool abort_done; }; =20 +struct geni_i2c_desc { + bool has_core_clk; + char *icc_ddr; + bool no_dma_support; + unsigned int tx_fifo_depth; +}; + struct geni_i2c_err_log { int err; const char *msg; @@ -764,6 +772,7 @@ static int geni_i2c_probe(struct platform_device *pdev) u32 proto, tx_depth, fifo_disable; int ret; struct device *dev =3D &pdev->dev; + const struct geni_i2c_desc *desc =3D NULL; =20 gi2c =3D devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); if (!gi2c) @@ -776,6 +785,14 @@ static int geni_i2c_probe(struct platform_device *pdev) if (IS_ERR(gi2c->se.base)) return PTR_ERR(gi2c->se.base); =20 + desc =3D device_get_match_data(&pdev->dev); + + if (desc && desc->has_core_clk) { + gi2c->core_clk =3D devm_clk_get(dev, "core"); + if (IS_ERR(gi2c->core_clk)) + return PTR_ERR(gi2c->core_clk); + } + gi2c->se.clk =3D devm_clk_get(dev, "se"); if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) return PTR_ERR(gi2c->se.clk); @@ -819,7 +836,7 @@ static int geni_i2c_probe(struct platform_device *pdev) gi2c->adap.dev.of_node =3D dev->of_node; strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); =20 - ret =3D geni_icc_get(&gi2c->se, "qup-memory"); + ret =3D geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory"); if (ret) return ret; /* @@ -829,12 +846,17 @@ static int geni_i2c_probe(struct platform_device *pde= v) */ gi2c->se.icc_paths[GENI_TO_CORE].avg_bw =3D GENI_DEFAULT_BW; gi2c->se.icc_paths[CPU_TO_GENI].avg_bw =3D GENI_DEFAULT_BW; - gi2c->se.icc_paths[GENI_TO_DDR].avg_bw =3D Bps_to_icc(gi2c->clk_freq_out); + if (!desc || desc->icc_ddr) + gi2c->se.icc_paths[GENI_TO_DDR].avg_bw =3D Bps_to_icc(gi2c->clk_freq_out= ); =20 ret =3D geni_icc_set_bw(&gi2c->se); if (ret) return ret; =20 + ret =3D clk_prepare_enable(gi2c->core_clk); + if (ret) + return ret; + ret =3D geni_se_resources_on(&gi2c->se); if (ret) { dev_err(dev, "Error turning on resources %d\n", ret); @@ -844,10 +866,15 @@ static int geni_i2c_probe(struct platform_device *pde= v) if (proto !=3D GENI_SE_I2C) { dev_err(dev, "Invalid proto %d\n", proto); geni_se_resources_off(&gi2c->se); + clk_disable_unprepare(gi2c->core_clk); return -ENXIO; } =20 - fifo_disable =3D readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO= _IF_DISABLE; + if (desc && desc->no_dma_support) + fifo_disable =3D false; + else + fifo_disable =3D readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIF= O_IF_DISABLE; + if (fifo_disable) { /* FIFO is disabled, so we can only use GPI DMA */ gi2c->gpi_mode =3D true; @@ -859,6 +886,16 @@ static int geni_i2c_probe(struct platform_device *pdev) } else { gi2c->gpi_mode =3D false; tx_depth =3D geni_se_get_tx_fifo_depth(&gi2c->se); + + /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ + if (!tx_depth && desc) + tx_depth =3D desc->tx_fifo_depth; + + if (!tx_depth) { + dev_err(dev, "Invalid TX FIFO depth\n"); + return -EINVAL; + } + gi2c->tx_wm =3D tx_depth - 1; geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, @@ -867,6 +904,7 @@ static int geni_i2c_probe(struct platform_device *pdev) dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); } =20 + clk_disable_unprepare(gi2c->core_clk); ret =3D geni_se_resources_off(&gi2c->se); if (ret) { dev_err(dev, "Error turning off resources %d\n", ret); @@ -932,6 +970,8 @@ static int __maybe_unused geni_i2c_runtime_suspend(stru= ct device *dev) gi2c->suspended =3D 1; } =20 + clk_disable_unprepare(gi2c->core_clk); + return geni_icc_disable(&gi2c->se); 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Tue, 29 Nov 2022 06:47:08 -0800 (PST) From: Neil Armstrong Date: Tue, 29 Nov 2022 15:47:06 +0100 Subject: [PATCH v3 6/6] i2c: qcom-geni: add support for I2C Master Hub variant MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-6-f6a20dc9996e@linaro.org> References: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-i2c-master-hub-v3-0-f6a20dc9996e@linaro.org> To: Bjorn Andersson , Rob Herring , Andy Gross , Krzysztof Kozlowski Cc: Krzysztof Kozlowski , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Add the I2C Master Hub serial engine compatible along the specific requirements in a new desc struct passed through the device match data. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/i2c/busses/i2c-qcom-geni.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 75dd0718c5a1..bfe75038bc14 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -1026,8 +1026,16 @@ static const struct dev_pm_ops geni_i2c_pm_ops =3D { NULL) }; =20 +const struct geni_i2c_desc i2c_master_hub =3D { + .has_core_clk =3D true, + .icc_ddr =3D NULL, + .no_dma_support =3D true, + .tx_fifo_depth =3D 16, +}; + static const struct of_device_id geni_i2c_dt_match[] =3D { { .compatible =3D "qcom,geni-i2c" }, + { .compatible =3D "qcom,geni-i2c-master-hub", .data =3D &i2c_master_hub }, {} }; MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); --=20 b4 0.10.1