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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:26 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] arm64: dts: rockchip: Enable GPU on SOQuartz CM4 Date: Sat, 12 Nov 2022 17:03:58 +0100 Message-Id: <20221112160404.70868-2-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This enables the Mali-G52 GPU on the SOQuartz CM4 module. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64= /boot/dts/rockchip/rk3566-soquartz.dtsi index 5bcd4be32964..6e99f049501c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -143,6 +143,11 @@ &gmac1m0_clkinout status =3D "disabled"; }; =20 +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + &i2c0 { status =3D "okay"; =20 --=20 2.38.1 From nobody Mon Apr 13 13:26:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3164CC4332F for ; Sat, 12 Nov 2022 16:04:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234739AbiKLQEk (ORCPT ); Sat, 12 Nov 2022 11:04:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234924AbiKLQEc (ORCPT ); Sat, 12 Nov 2022 11:04:32 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBC121409B; Sat, 12 Nov 2022 08:04:30 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id a11-20020a05600c2d4b00b003cf6f5fd9f1so4942780wmg.2; Sat, 12 Nov 2022 08:04:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ryja4COVOHIl0RDlGLdndcpFHG6CZ7IIZjln1Zob1wI=; b=W2+hFqYRrsHwvKIwFlXxU5UeP4Hn1PIXuemAtrwiCMuoPIps/J5IVBDmvBBC4QGkK4 CJ4sb8OTYws5/48bkUAK0jT2+pQLyZFuTR72CQG/j4Byb9OmhHG2NpcmEBdFLbkixVOB 2QpBaPlJfxIyTGFSpliQdcGPJLlXE4gSNJAvc3L9qQP2TFgg5ZAF3RG48z+iF4U9dTjD 4eOa/JQ09vIXymtES2xkBSZW/FG/EZIXkXDp4a0E9QUeJmYOxODQSS3dIYVmevD4FMT6 Tf8mOVHPnr7KkC8NaqFZ2XVn5CJIQWi12qxYvUC2/94qD750jO+OWr6GJgXw2n7i4ZnU GYzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ryja4COVOHIl0RDlGLdndcpFHG6CZ7IIZjln1Zob1wI=; b=mV/9NxnltUg5CXrrhiW6eoVdHiszzvdEcCEVXUst10NEEtuU3+++ScNgBIRXD+B44v L0bygiy/GwZFlSbDlHxAS38jWV5kZEAO8XBJwCkLgDjRg8hGQlAOLn3JOyTfO5pCuDCd fHQJuzqFGqUG59lI07NveJmW8BLTLsD10kFokW6U5U3H52/lp4Y2vv++fHWUB+kbTz7q 0WIAWmSYPK22V9WT/zMMFOEcfzU/Eer9M6LeKgvcYm+n6OPsA3Mpc2Q/E1e6Ut1BGbs3 H/O18fK6W2A6x9qFFEWNc+4+hIP9jMxNbxIHT8BRckn3YBPA2s0ObMCRYNrdPAiKgtlL 3fBQ== X-Gm-Message-State: ANoB5pn484sva+UZR66l2LzKyAB0QYpNE/yPocx13SPPf7Ila35Z4fnk Zh+3MtPJEIROyiTgI/rAqHc6VwcVyXE= X-Google-Smtp-Source: AA0mqf7R3EjsE/f2MM3c5yicPRNoufA1vOUCZrRluhmusrV6myk9zahbFvRQoaRlG3nOijvjuvx5mA== X-Received: by 2002:a7b:cd0e:0:b0:3cf:ca45:3b19 with SMTP id f14-20020a7bcd0e000000b003cfca453b19mr4057679wmj.179.1668269069370; Sat, 12 Nov 2022 08:04:29 -0800 (PST) Received: from localhost.localdomain (84-72-105-84.dclient.hispeed.ch. [84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:28 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] arm64: dts: rockchip: Enable video output and HDMI on SOQuartz Date: Sat, 12 Nov 2022 17:03:59 +0100 Message-Id: <20221112160404.70868-3-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds and enables the necessary device tree nodes to enable video output and HDMI functionality on the SOQuartz module. Signed-off-by: Nicolas Frattaroli --- .../boot/dts/rockchip/rk3566-soquartz.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64= /boot/dts/rockchip/rk3566-soquartz.dtsi index 6e99f049501c..0bfb0cea7d6b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -4,6 +4,7 @@ =20 #include #include +#include #include "rk3566.dtsi" =20 / { @@ -28,6 +29,17 @@ gmac1_clkin: external-gmac1-clock { #clock-cells =3D <0>; }; =20 + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + leds { compatible =3D "gpio-leds"; =20 @@ -148,6 +160,24 @@ &gpu { status =3D "okay"; }; =20 +&hdmi { + avdd-0v9-supply =3D <&vdda0v9_image>; + avdd-1v8-supply =3D <&vcca1v8_image>; + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + &i2c0 { status =3D "okay"; =20 @@ -619,3 +649,20 @@ &usb2phy0_otg { &usb_host0_xhci { status =3D "disabled"; }; + +&vop { + assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; --=20 2.38.1 From nobody Mon Apr 13 13:26:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78906C4332F for ; Sat, 12 Nov 2022 16:04:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235015AbiKLQEp (ORCPT ); Sat, 12 Nov 2022 11:04:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232347AbiKLQEd (ORCPT ); Sat, 12 Nov 2022 11:04:33 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FC79193C6; Sat, 12 Nov 2022 08:04:32 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id w14so10154966wru.8; Sat, 12 Nov 2022 08:04:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ijKNfiunV63AFU9RzYinLsQfMGW1tKqr0LKOgrxroKY=; b=HH+eoyr8wWz+PKf3eTxeIrPtgd+VdxvgSfFjHy3RdnzKHzXvFhUscCZ8oBFmTOtyOV +itCm1tI1JznZHo0CX+0nf+J8urzmatqkiF+mF9rKFLNYMjTbheGHW4U/E+CqtFePiWE tqfkb/yWDzao3xg0A+DgJ93jGHsSEiW8dc0Ha1YfwQpTQ+osNVt59Wj53xotk3VATra8 6okQ4A1FUnSULA/EW9Inh5ff24nvOqJ8Xw4kbB/b5f1N8lIImEVt3bB9B1BjyZG5a6dA Z+QvMK8IB132LL6pQTOrVLfZBlGmz3MTsmfbWMn7n7ZvgnyasPC5WIgr8IyP7SMX3hbZ 6UsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ijKNfiunV63AFU9RzYinLsQfMGW1tKqr0LKOgrxroKY=; b=uLSJ1GE9SchN11n/44k+1Baos+timqilacM9Spa25M5v3aVsmM4BJwm/s30H5aTWsP waUoqqsWaTahr4B56UjTxLXaSpsFyHgOH4wuQjEYpsh/YJJQR0pc2E0vhKr/KtKlpLYp +EfWxHwLiB7EzLudy8X6ASoz3JzBNoGsHfVL7v6vekPJBCMqvMuNW3MA6V3YF2dxsXVF yEm/enhSPQcC7NqP1Fa8Bp0G5e0otvOcI9ijHESUppneJ6El8sZFco7ddpegf+6poGwa f+g+j+p2WF7PRaD80Nla3jKUcJ/7VJS5+sUFlc7CnbpkVZ/2jdQPtNtKoc+RHI3PeJ4R 588A== X-Gm-Message-State: ANoB5pn+OtWjpuXbRZ8VoP+W9BwoD0nB4JMcqJVF/n1GyQLrChPAVtE/ iL/ilpCcrqw4w9MsExYqqvw= X-Google-Smtp-Source: AA0mqf5rGZgCxdHJ6sUSJMm0IUngegN+ozLvYpNtMPG23JIot08oGXa88eYC1GzUoEmMHusXvXgh2Q== X-Received: by 2002:adf:fbc6:0:b0:22e:3392:fb46 with SMTP id d6-20020adffbc6000000b0022e3392fb46mr3627992wrs.706.1668269070882; Sat, 12 Nov 2022 08:04:30 -0800 (PST) Received: from localhost.localdomain (84-72-105-84.dclient.hispeed.ch. [84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:30 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] arm64: dts: rockchip: Enable HDMI sound on SOQuartz Date: Sat, 12 Nov 2022 17:04:00 +0100 Message-Id: <20221112160404.70868-4-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch enables the i2s0 node on SOQuartz, which is responsible for hdmi audio, and adds an hdmi-sound node to enable said audio. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64= /boot/dts/rockchip/rk3566-soquartz.dtsi index 0bfb0cea7d6b..1b975822effa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -178,6 +178,10 @@ hdmi_out_con: endpoint { }; }; =20 +&hdmi_sound { + status =3D "okay"; +}; + &i2c0 { status =3D "okay"; =20 @@ -446,6 +450,10 @@ &i2c4 { status =3D "disabled"; }; =20 +&i2s0_8ch { + status =3D "okay"; +}; + /* * i2s1_8ch is exposed on CM1 / Module1A * pin 24 - i2s1_sdi1_m1 --=20 2.38.1 From nobody Mon Apr 13 13:26:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E21BCC4332F for ; Sat, 12 Nov 2022 16:04:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234970AbiKLQEt (ORCPT ); Sat, 12 Nov 2022 11:04:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234953AbiKLQEe (ORCPT ); Sat, 12 Nov 2022 11:04:34 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D869E1403A; Sat, 12 Nov 2022 08:04:33 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id bs21so10178166wrb.4; Sat, 12 Nov 2022 08:04:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oJ27VAZylslPL3euOsLLalZQXH6wtWYg2Z/Is/uMUw0=; b=HKKk23/nYx4DzhMOBDXtEJ3NKcPfdpwCTM3sBx8NmGDUwGFSQeFAq6goYAq8CgtD2H Woq/th/pi/l9XsIFlLg2yV7Z+aDEQ+4OpMx9Z6Tnbu+QrSqubiPGyo7w3IzX9rsCdC4d TCssYdAC1rlqCk0+DkL9k7x2tFd2PPo4l0/q8nj8AR8oXUWC4VA4lJxTApV1GIHe6IOj /U6oHgDf593VFuHct8gBMk6JoXAeICQSVOLXAM+gu1zOm9BdKPJELZC/hfJ5hHUhTxXO wmVBqSKQtmONK4g5+EVlk/hvJ5x7nab4ZZBs3Nt/bWa+x1o0iXJ2X7RF1RPjsElLf6Nr m8zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oJ27VAZylslPL3euOsLLalZQXH6wtWYg2Z/Is/uMUw0=; b=whPMx7TPDxKOk6RlPVWnew22Ttq7bvTJa05/pgB9/WotJ1AHrCyXUGKieQtXAJefZg v4OX1d5101+c89Tvs3wCwtoge9SJPNNO5zozgf+gzqvV4C01Dp43tQPP9UX2vPZyqxpq AlFD5dN4OYKfFR0dVHHtkDS9xvTjvrjncE3tzHEFEnYsuIXNyUcCi+WIiRT9dW/pWavz DG7a+vTAJogPpFiK/q/iQlAtzPGPqaXaSmDutxcL+GcASDbLp6k0HjdP5QzoD91malbm EyxLqS8nUZGYL3iesM5FWg1rWoG76shMfk94qz4DJwRFFFvB+0BoWVhEYFFKvOanrso5 4PvQ== X-Gm-Message-State: ANoB5pmMDULEpnuvGCzDHcltWrBgjxae79etOZztxX5rBtSb9AfLrYem 9qo3Dd5mM6EztyutijQRFWE= X-Google-Smtp-Source: AA0mqf4LLDY4KIu9pV27y1Mc+ZPFwpD7rdhFe1DVUzoLHJLMxxyOLvmhrL7M3GBqWzoOAhHTrlBGEQ== X-Received: by 2002:a5d:4f05:0:b0:241:8103:766d with SMTP id c5-20020a5d4f05000000b002418103766dmr911326wru.386.1668269072512; Sat, 12 Nov 2022 08:04:32 -0800 (PST) Received: from localhost.localdomain (84-72-105-84.dclient.hispeed.ch. [84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:32 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO Date: Sat, 12 Nov 2022 17:04:01 +0100 Message-Id: <20221112160404.70868-5-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch enables the PCIe2 on the CM4IO board when paired with a SOQuartz CM4 System-on-Module board. combphy2 also needs to be enabled in this case to make the PHY work for this. Signed-off-by: Nicolas Frattaroli --- .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 15 +++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/ar= m64/boot/dts/rockchip/rk3566-soquartz-cm4.dts index e00568a6be5c..263ce40770dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -30,6 +30,12 @@ vcc_5v: vcc-5v-regulator { }; }; =20 +/* phy for pcie */ +&combphy2 { + phy-supply =3D <&vcc3v3_sys>; + status =3D "okay"; +}; + &gmac1 { status =3D "okay"; }; @@ -105,6 +111,11 @@ &led_work { status =3D "okay"; }; =20 +&pcie2x1 { + vpcie3v3-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + &rgmii_phy1 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64= /boot/dts/rockchip/rk3566-soquartz.dtsi index 1b975822effa..ce7165d7f1a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -487,6 +487,12 @@ rgmii_phy1: ethernet-phy@0 { }; }; =20 +&pcie2x1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_reset_h>; + reset-gpios =3D <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -512,6 +518,15 @@ diy_led_enable_h: diy-led-enable-h { }; }; =20 + pcie { + pcie_clkreq_h: pcie-clkreq-h { + rockchip,pins =3D <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_reset_h: pcie-reset-h { + rockchip,pins =3D <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; --=20 2.38.1 From nobody Mon Apr 13 13:26:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A05F7C43217 for ; Sat, 12 Nov 2022 16:04:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234953AbiKLQEx (ORCPT ); Sat, 12 Nov 2022 11:04:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234961AbiKLQEg (ORCPT ); Sat, 12 Nov 2022 11:04:36 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 712E6193C7; Sat, 12 Nov 2022 08:04:35 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id p13-20020a05600c468d00b003cf8859ed1bso4946416wmo.1; Sat, 12 Nov 2022 08:04:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oo1e2pdndrGc6hVcKePpw8O0AQvGqHawFLLzPC17yeY=; b=pP5PuMeTMje8MHtJrs+dShOCpQSTLDpgsZzH09YamX+H1RoikyDCjlk9vvfHT2/aMU FiWuOMH7TsXRfzFC5GfrEoCvF/NRd64KxpbkWtgMVsIyDVgHIh05Fz4jrlvmjswSPeB9 AInStLhIx08ygaA4RWh9iPga0eID/dZM9qYqn1zDR4bOKsVX17XcTHGQ7U+Z7SjlSaJ1 SGkQQOdqktLJCOWzbuQIe3RjL8hQILzEOr0/mp88mKElGzqKho4yxJZMclHdb/7Urty0 2DTGpD2IHN1Z4nZ9838i/YtDtwrhqRU6lRKsHsicqpZva9vwfrUEa2NuPUmGtaUlbwkY 5ttA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oo1e2pdndrGc6hVcKePpw8O0AQvGqHawFLLzPC17yeY=; b=YgaWYmTb/pBn3vIH2k8MruUjvykzJFwyxt0ppx3768ohxkKZqYGK/foLCVj9lgXkIx wp2zwpsTE84m0t45cRnFn/vKo/CLNWy6iZbxLgFeso9SpORob0lE+TfVPM6MDzZxRGWR Kw4lIT3muJBpo5KROJWif7Duti+uLIYhJDOyZqpoXcoYQ/0N4VBDXCdhpkYcYc0d20Ej rSlm3eUx7x5KzKTe1/TKYtiNMh2KGkVQkTrH4RimkONbsdTE4hQS3W1g1wSzRqpOmXAT fVgnrZGFPGN2v8XTvL4tAtIQz3PWNdkBO1C9ASQqCNiFl773RNWt92rz9Qx6Sz5U0YKm EcTQ== X-Gm-Message-State: ANoB5pkKskMCjXis0unJb4gJDRDmne0ZO3xSmuH+1i1mH3XMxdOk2S9b X+TBlFQ5lkNoWMeS8xIVPiA= X-Google-Smtp-Source: AA0mqf6gNkLJsyCFH5GzLpe8VqEmtAK/h1PHEytwQxLYAAuYv407DsjfvhExhFcj2H9GE3FK/R86DA== X-Received: by 2002:a05:600c:4b16:b0:3cf:77a6:2c2e with SMTP id i22-20020a05600c4b1600b003cf77a62c2emr4084324wmp.179.1668269074086; Sat, 12 Nov 2022 08:04:34 -0800 (PST) Received: from localhost.localdomain (84-72-105-84.dclient.hispeed.ch. [84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:33 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] dt-bindings: arm: rockchip: Add SOQuartz Blade Date: Sat, 12 Nov 2022 17:04:02 +0100 Message-Id: <20221112160404.70868-6-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Signed-off-by: Nicolas Frattaroli --- Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 244c42eaae8c..fc5f14fcd007 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -579,6 +579,7 @@ properties: items: - enum: - pine64,soquartz-cm4io + - pine64,soquartz-blade - const: pine64,soquartz - const: rockchip,rk3566 =20 --=20 2.38.1 From nobody Mon Apr 13 13:26:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9293CC4332F for ; Sat, 12 Nov 2022 16:04:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234969AbiKLQE5 (ORCPT ); Sat, 12 Nov 2022 11:04:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234946AbiKLQEi (ORCPT ); Sat, 12 Nov 2022 11:04:38 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9366119C25; Sat, 12 Nov 2022 08:04:37 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id p13-20020a05600c468d00b003cf8859ed1bso4946457wmo.1; Sat, 12 Nov 2022 08:04:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9FPqSrntXIQJ+cahpoCu9kmTaZguFXQ3wH0XIA4kS/o=; b=mheZ7yHlypaukxwCu2bImvYh8XQskT9PvWpzYzRRjAixOUXWLXHfp8lDZXLW6GXha3 iU7XJ6zltMdpL3n+BzR4M9640o5YdhX1nVlqpR2muA7W4EC5Mip9Qsh/wbCywtDEbDeI zqS2fBFZ8Dvob5fh7mtUOHnU23BvEOcbPx0a78CG5A0YE+ZbzVEEQh9WRwqC/XxHtzSc Qwy30QMtqgfESqMg9+BaWSIgMnRsccsPBguSHO7QGIa+myIzYwdTymefb7uYRZMRhOB5 GG/L0jBMQ6Jp3Hf2jrMprRtoMADORKafov/DvedutXyXXeXR9BmTdJGKu/avPxmOnrN0 5tIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9FPqSrntXIQJ+cahpoCu9kmTaZguFXQ3wH0XIA4kS/o=; b=fVXF+mZGk0g0yKJAoUNMJivzSDb8ULudjBZ/aprzz/SVIGW7Bmr53Xg2L3edtmJrru zrv90voqBGTx0Tf8M0MZUowqnDeW1RqN8P1uYe5f51prf/ylsoS33UDxtfhjfBsgSfnP MrBS3JynmN2uQ758jWmOJRXq1cSqFpvg6wteZvr2b1/lerp6maKM6OvtWfF2o/U9svKj q28jFmwKydhK2gMx4Q+ifKRnCZvIRw0qMZQvlkefhijs8ZBO2wgEswL17bT8WD36w7HJ Jj2hYk/OKXyxImmphNalHHPikmLViW/h2hcqGF+JuKcg2X2/BHqPL28JVPHBlYTFcMcq aSig== X-Gm-Message-State: ANoB5pnsvk3DvmpZXi05bUpm0suOt4n+2u1UNwOnREfdHeTL4W/y0mjE muUSM1L3dy/igqrvHa3QqaE= X-Google-Smtp-Source: AA0mqf57g76RoRF5m02yDFXD3u+BYjAgTRAZxyQWAQQRdUIH0rePDegYsPRl4GnduGxh+7dPTYH+mg== X-Received: by 2002:a05:600c:54c1:b0:3c6:e471:7400 with SMTP id iw1-20020a05600c54c100b003c6e4717400mr4201425wmb.98.1668269076198; Sat, 12 Nov 2022 08:04:36 -0800 (PST) Received: from localhost.localdomain (84-72-105-84.dclient.hispeed.ch. [84.72.105.84]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003cf87623c16sm14605752wmb.4.2022.11.12.08.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 08:04:35 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Andrew Powers-Holmes , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] arm64: dts: rockchip: Add SOQuartz blade board Date: Sat, 12 Nov 2022 17:04:03 +0100 Message-Id: <20221112160404.70868-7-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> References: <20221112160404.70868-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Andrew Powers-Holmes This adds a device tree for the PINE64 SOQuartz blade baseboard, a 1U rack mountable baseboard for the CM4 form factor with PoE support designed for the SOQuartz CM4 System-on-Module. The board takes power from either PoE or a 5V DC input, and allows for mounting an M.2 SSD. The board also features one USB 2.0 host port, one HDMI output, a 3.5mm jack for UART, and the aforementioned gigabit networking port. Signed-off-by: Andrew Powers-Holmes [rebase, squash, reword, misc fixes] Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ 2 files changed, 195 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 50942086490d..2157f086c59e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/= arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts new file mode 100644 index 000000000000..4e49bebf548b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include + +#include "rk3566-soquartz.dtsi" + +/ { + model =3D "PINE64 RK3566 SOQuartz on Blade carrier board"; + compatible =3D "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk35= 66"; + + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + /* labeled VCC_SSD in schematic */ + vcc3v3_pcie_p: vcc3v3-pcie-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vbus>; + }; + + vcc5v_dcin: vcc5v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; +}; + +&combphy2 { + phy-supply =3D <&vcc3v3_sys>; + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status =3D "okay"; + +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status =3D "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status =3D "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status =3D "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status =3D "disabled"; +}; + +&led_diy { + color =3D ; + function =3D LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger =3D "disk-activity"; + status =3D "okay"; +}; + +&led_work { + color =3D ; + function =3D LED_FUNCTION_STATUS; + linux,default-trigger =3D "heartbeat"; + status =3D "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply =3D <&vcc3v3_pcie_p>; + status =3D "okay"; +}; + +&rgmii_phy1 { + status =3D "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status =3D "disabled"; +}; + +&sdmmc0 { + vmmc-supply =3D <&vcc3v0_sd>; + status =3D "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status =3D "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status =3D "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vbus>; + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&vbus { + vin-supply =3D <&vcc5v_dcin>; +}; --=20 2.38.1