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[119.18.16.128]) by smtp.gmail.com with ESMTPSA id e2-20020aa79802000000b0056e8ce106d1sm3132091pfl.132.2022.11.12.03.42.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 03:42:10 -0800 (PST) From: Andrew Powers-Holmes To: linux-rockchip@lists.infradead.org Cc: =?UTF-8?q?Ond=C5=99ej=20Jirman?= , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Peter Geis , Frank Wunderlich , Michael Riesch , Yifeng Zhao , Sascha Hauer , Nicolas Frattaroli , Chris Morgan , Ezequiel Garcia , Robin Murphy , Mark Kettenis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/1] arm64: dts: rockchip: rk356x: Fix PCIe register and range mappings Date: Sat, 12 Nov 2022 22:41:26 +1100 Message-Id: <20221112114125.1637543-2-aholmes@omnom.net> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221112114125.1637543-1-aholmes@omnom.net> References: <20221112114125.1637543-1-aholmes@omnom.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The register and range mappings for the PCIe controller in Rockchip's RK356x SoCs are incorrect. Replace them with corrected values from the vendor BSP sources, updated to match current DT schema. Tested-by: Ondrej Jirman Signed-off-by: Andrew Powers-Holmes --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++--- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts= /rockchip/rk3568.dtsi index ba67b58f05b7..c1128d0c4406 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -94,9 +94,10 @@ pcie3x1: pcie@fe270000 { power-domains =3D <&power RK3568_PD_PIPE>; reg =3D <0x3 0xc0400000 0x0 0x00400000>, <0x0 0xfe270000 0x0 0x00010000>, - <0x3 0x7f000000 0x0 0x01000000>; - ranges =3D <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, - <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; + <0x0 0xf2000000 0x0 0x00100000>; + ranges =3D <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; reg-names =3D "dbi", "apb", "config"; resets =3D <&cru SRST_PCIE30X1_POWERUP>; reset-names =3D "pipe"; @@ -146,9 +147,10 @@ pcie3x2: pcie@fe280000 { power-domains =3D <&power RK3568_PD_PIPE>; reg =3D <0x3 0xc0800000 0x0 0x00400000>, <0x0 0xfe280000 0x0 0x00010000>, - <0x3 0xbf000000 0x0 0x01000000>; - ranges =3D <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, - <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; + <0x0 0xf2000000 0x0 0x01000000>; + ranges =3D <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; reg-names =3D "dbi", "apb", "config"; resets =3D <&cru SRST_PCIE30X2_POWERUP>; reset-names =3D "pipe"; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts= /rockchip/rk356x.dtsi index 164708f1eb67..eec1d496c617 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -951,7 +951,7 @@ pcie2x1: pcie@fe260000 { compatible =3D "rockchip,rk3568-pcie"; reg =3D <0x3 0xc0000000 0x0 0x00400000>, <0x0 0xfe260000 0x0 0x00010000>, - <0x3 0x3f000000 0x0 0x01000000>; + <0x0 0xf4000000 0x0 0x00100000>; reg-names =3D "dbi", "apb", "config"; interrupts =3D , , @@ -980,8 +980,9 @@ pcie2x1: pcie@fe260000 { phys =3D <&combphy2 PHY_TYPE_PCIE>; phy-names =3D "pcie-phy"; power-domains =3D <&power RK3568_PD_PIPE>; - ranges =3D <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 - 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; + ranges =3D <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; resets =3D <&cru SRST_PCIE20_POWERUP>; reset-names =3D "pipe"; #address-cells =3D <3>; -- 2.38.0