From nobody Sat Sep 21 11:45:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 505DAC4332F for ; Thu, 10 Nov 2022 06:37:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232305AbiKJGhe (ORCPT ); Thu, 10 Nov 2022 01:37:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232505AbiKJGh3 (ORCPT ); Thu, 10 Nov 2022 01:37:29 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD9B62CE09; Wed, 9 Nov 2022 22:37:24 -0800 (PST) X-UUID: 84fcb39d4bea492493923d02ce175217-20221110 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IYNsu3+YhsLdxa/TdV8zExfZobnqiPHL5UL2NPZZAqU=; b=YImq3n3hByXXLCJE79wAdUBeJXRNslKfuWyZiU0Yhz56pGZfe6ktluQcsUQYJNOZ9JSgY+wq9ErYcvZMLXS09af7XOo2Q0WOpg9re4otSaueCrQibWsK5vKokwS/KSGr0vgOGhke92EuRYeViY4JDKUWxaN/vCZLiogqvAplE8w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:7b107302-070d-47e8-8e77-fe11386b47ab,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:62cd327,CLOUDID:9e12e350-b7af-492d-8b40-b1032f90ce11,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 84fcb39d4bea492493923d02ce175217-20221110 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1855394692; Thu, 10 Nov 2022 14:37:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 10 Nov 2022 14:37:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 10 Nov 2022 14:37:18 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v4 1/4] arm64: dts: mt8195: Add dp-intf nodes Date: Thu, 10 Nov 2022 14:37:13 +0800 Message-ID: <20221110063716.25677-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221110063716.25677-1-rex-bc.chen@mediatek.com> References: <20221110063716.25677-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 nodes. Dp-intf0 is for edptx and dp-intf1 is for dptx. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 2edfc21ece56..c380738d10cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2094,6 +2094,17 @@ mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; =20 + dp_intf0: dp-intf@1c015000 { + compatible =3D "mediatek,mt8195-dp-intf"; + reg =3D <0 0x1c015000 0 0x1000>; + interrupts =3D ; + clocks =3D <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names =3D "engine", "pixel", "pll"; + status =3D "disabled"; + }; + mutex: mutex@1c016000 { compatible =3D "mediatek,mt8195-disp-mutex"; reg =3D <0 0x1c016000 0 0x1000>; @@ -2182,5 +2193,17 @@ clock-names =3D "apb", "smi", "gals"; power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + + dp_intf1: dp-intf@1c113000 { + compatible =3D "mediatek,mt8195-dp-intf"; + reg =3D <0 0x1c113000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks =3D <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names =3D "engine", "pixel", "pll"; + status =3D "disabled"; + }; }; }; --=20 2.18.0