From nobody Sat Sep 21 09:51:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 505DAC4332F for ; Thu, 10 Nov 2022 06:37:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232305AbiKJGhe (ORCPT ); Thu, 10 Nov 2022 01:37:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232505AbiKJGh3 (ORCPT ); Thu, 10 Nov 2022 01:37:29 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD9B62CE09; Wed, 9 Nov 2022 22:37:24 -0800 (PST) X-UUID: 84fcb39d4bea492493923d02ce175217-20221110 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IYNsu3+YhsLdxa/TdV8zExfZobnqiPHL5UL2NPZZAqU=; b=YImq3n3hByXXLCJE79wAdUBeJXRNslKfuWyZiU0Yhz56pGZfe6ktluQcsUQYJNOZ9JSgY+wq9ErYcvZMLXS09af7XOo2Q0WOpg9re4otSaueCrQibWsK5vKokwS/KSGr0vgOGhke92EuRYeViY4JDKUWxaN/vCZLiogqvAplE8w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:7b107302-070d-47e8-8e77-fe11386b47ab,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:62cd327,CLOUDID:9e12e350-b7af-492d-8b40-b1032f90ce11,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 84fcb39d4bea492493923d02ce175217-20221110 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1855394692; Thu, 10 Nov 2022 14:37:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 10 Nov 2022 14:37:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 10 Nov 2022 14:37:18 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v4 1/4] arm64: dts: mt8195: Add dp-intf nodes Date: Thu, 10 Nov 2022 14:37:13 +0800 Message-ID: <20221110063716.25677-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221110063716.25677-1-rex-bc.chen@mediatek.com> References: <20221110063716.25677-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 nodes. Dp-intf0 is for edptx and dp-intf1 is for dptx. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 2edfc21ece56..c380738d10cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2094,6 +2094,17 @@ mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; =20 + dp_intf0: dp-intf@1c015000 { + compatible =3D "mediatek,mt8195-dp-intf"; + reg =3D <0 0x1c015000 0 0x1000>; + interrupts =3D ; + clocks =3D <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names =3D "engine", "pixel", "pll"; + status =3D "disabled"; + }; + mutex: mutex@1c016000 { compatible =3D "mediatek,mt8195-disp-mutex"; reg =3D <0 0x1c016000 0 0x1000>; @@ -2182,5 +2193,17 @@ clock-names =3D "apb", "smi", "gals"; power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + + dp_intf1: dp-intf@1c113000 { + compatible =3D "mediatek,mt8195-dp-intf"; + reg =3D <0 0x1c113000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks =3D <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names =3D "engine", "pixel", "pll"; + status =3D "disabled"; + }; }; }; --=20 2.18.0 From nobody Sat Sep 21 09:51:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3503C433FE for ; Thu, 10 Nov 2022 06:37:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232541AbiKJGhk (ORCPT ); Thu, 10 Nov 2022 01:37:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232509AbiKJGh3 (ORCPT ); Thu, 10 Nov 2022 01:37:29 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA3F42CE07; Wed, 9 Nov 2022 22:37:23 -0800 (PST) X-UUID: 36bc58a447eb43bfa44a11f2f46079b6-20221110 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=d7zkDnaWEabyE5XdwVr4ccYWpjzTXOcJn5mpauaL9LQ=; b=eS+UP88zr6TB3FWCnaXYoj/F6JJavvVbvhcUzv2BzB5myEz8Op2N3A/LR/ec9+KeDufd8gCvmX7DTPexRKRW77B8FDM8as+40pnyXvmoO/mKudAJbp/5CQCmoe/he/dF15Zvn9qR+a0Eh9TpV8XhdnPSgWH3oYcMhnZ4nWxNcCA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:b8dea487-a329-4893-9474-a8dc4b9bd756,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.12,REQID:b8dea487-a329-4893-9474-a8dc4b9bd756,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:62cd327,CLOUDID:6099de85-088c-4756-8f76-577be701e693,B ulkID:221110143719DAY63BKH,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 36bc58a447eb43bfa44a11f2f46079b6-20221110 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 460132987; Thu, 10 Nov 2022 14:37:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 10 Nov 2022 14:37:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 10 Nov 2022 14:37:18 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v4 2/4] arm64: dts: mt8195: Add edptx and dptx nodes Date: Thu, 10 Nov 2022 14:37:14 +0800 Message-ID: <20221110063716.25677-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221110063716.25677-1-rex-bc.chen@mediatek.com> References: <20221110063716.25677-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MT8195, we use edptx as the internal display interface and use dptx as the external display interface. Therefore, we need to add these nodes to support the internal display and the external display. - Add dp calibration data in the efuse node. - Add edptx and dptx nodes for MT8195. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index c380738d10cb..7acbef5a4517 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1244,6 +1244,9 @@ reg =3D <0x189 0x2>; bits =3D <7 5>; }; + dp_calibration: dp-data@1ac { + reg =3D <0x1ac 0x10>; + }; }; =20 u3phy2: t-phy@11c40000 { @@ -2205,5 +2208,27 @@ clock-names =3D "engine", "pixel", "pll"; status =3D "disabled"; }; + + edp_tx: edp-tx@1c500000 { + compatible =3D "mediatek,mt8195-edp-tx"; + reg =3D <0 0x1c500000 0 0x8000>; + nvmem-cells =3D <&dp_calibration>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts =3D ; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible =3D "mediatek,mt8195-dp-tx"; + reg =3D <0 0x1c600000 0 0x8000>; + nvmem-cells =3D <&dp_calibration>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts =3D ; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; }; }; --=20 2.18.0 From nobody Sat Sep 21 09:51:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0F3AC433FE for ; Thu, 10 Nov 2022 06:37:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229585AbiKJGhn (ORCPT ); Thu, 10 Nov 2022 01:37:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232511AbiKJGh3 (ORCPT ); Thu, 10 Nov 2022 01:37:29 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E02972CE0D; Wed, 9 Nov 2022 22:37:25 -0800 (PST) X-UUID: 24eb4841f3cc46beb9c8849fb360f3d7-20221110 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=g8vhFKeVZODszpNNdcs1n44q8B0+ixfLD0v3NWycG2k=; b=IBiW34Q24VMck8asBhnkcKvtdizaveZPW063PBBUXsj5mA2TMQCVtbNIHg4E4v0uHZDJZpkvZI99s3B2yggzLXN7ICkyAC22PjKGTuRBdxNaOsYD+vs6tIt0m81yN0xnkEIBym9qKKZO4hfJFLZZ56Yn1Pjx6+MrFeq8gENfJHk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:87e851d3-3cef-43c8-8af5-35150a4cc7b9,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:62cd327,CLOUDID:66b9265d-100c-4555-952b-a62c895efded,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 24eb4841f3cc46beb9c8849fb360f3d7-20221110 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 670770188; Thu, 10 Nov 2022 14:37:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 10 Nov 2022 14:37:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 10 Nov 2022 14:37:18 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v4 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports Date: Thu, 10 Nov 2022 14:37:15 +0800 Message-ID: <20221110063716.25677-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221110063716.25677-1-rex-bc.chen@mediatek.com> References: <20221110063716.25677-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 ports. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- .../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 9b62e161db26..303dc32c64dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -120,6 +120,24 @@ }; }; =20 +&dp_intf0 { + status =3D "okay"; + + port { + dp_intf0_out: endpoint { + }; + }; +}; + +&dp_intf1 { + status =3D "okay"; + + port { + dp_intf1_out: endpoint { + }; + }; +}; + &i2c0 { status =3D "okay"; =20 --=20 2.18.0 From nobody Sat Sep 21 09:51:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8BCDC43219 for ; Thu, 10 Nov 2022 06:37:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232517AbiKJGhb (ORCPT ); Thu, 10 Nov 2022 01:37:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232471AbiKJGh1 (ORCPT ); Thu, 10 Nov 2022 01:37:27 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB8562CDFB; Wed, 9 Nov 2022 22:37:22 -0800 (PST) X-UUID: 5c24d21a09404077a48aa50daced8de0-20221110 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=o4SwcYmQeEsPhNZNiOlAz3LSIKt52BQiCkN0gMjK+lM=; b=ZkKnoofum6hASHZt3TZG5BNd4iNfpwShZ/FMMGsAyaKsywM8huesT3wOzfQd0ei9hb2pXrHwFofmV5uurhpCIpH2nN6rr+h1Vz/7lDIwX1mmkkkGTsnJkWWAZ+tv0Cr28Rsp5SVSRG5u/Gjr4XosOaQNJZTISgClDnhUZNbkg/U=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:7d90d25e-dfd1-4590-8ace-0e558026d7f5,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:62cd327,CLOUDID:5f99de85-088c-4756-8f76-577be701e693,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 5c24d21a09404077a48aa50daced8de0-20221110 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1697423243; Thu, 10 Nov 2022 14:37:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 10 Nov 2022 14:37:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 10 Nov 2022 14:37:18 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v4 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support Date: Thu, 10 Nov 2022 14:37:16 +0800 Message-ID: <20221110063716.25677-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221110063716.25677-1-rex-bc.chen@mediatek.com> References: <20221110063716.25677-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In cherry projects, we use edptx as the internal display interface and use dptx as the external display interface. To support this, we need to add more properties. - Add pinctrls for edptx and dptx. - Add ports for edptx and dptx. The port connections for the internal and external display: dp-intf0 -> edptx -> panel dp-intf1 -> dptx The edptx endpoint is kept empty for now, as the panel addition will come in a later commit. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 303dc32c64dc..560103e29017 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -125,6 +125,7 @@ =20 port { dp_intf0_out: endpoint { + remote-endpoint =3D <&edp_in>; }; }; }; @@ -134,6 +135,59 @@ =20 port { dp_intf1_out: endpoint { + remote-endpoint =3D <&dptx_in>; + }; + }; +}; + +&edp_tx { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edptx_pins_default>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + edp_in: endpoint { + remote-endpoint =3D <&dp_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + edp_out: endpoint { + data-lanes =3D <0 1 2 3>; + }; + }; + }; +}; + +&dp_tx { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dptx_pin>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dptx_in: endpoint { + remote-endpoint =3D <&dp_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dptx_out: endpoint { + data-lanes =3D <0 1 2 3>; + }; }; }; }; @@ -497,6 +551,20 @@ }; }; =20 + edptx_pins_default: edptx-default-pins { + pins-cmd-dat { + pinmux =3D ; + bias-pull-up; + }; + }; + + dptx_pin: dptx-default-pins { + pins-cmd-dat { + pinmux =3D ; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux =3D , --=20 2.18.0