From nobody Mon Dec 15 01:32:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF35CC4332F for ; Thu, 10 Nov 2022 01:57:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232394AbiKJB5D (ORCPT ); Wed, 9 Nov 2022 20:57:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232024AbiKJB4j (ORCPT ); Wed, 9 Nov 2022 20:56:39 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFED43055D; Wed, 9 Nov 2022 17:56:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668045369; x=1699581369; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Aa+hmfCC+4pXGPdI3/P0Vz02MWKoodX4VOXGoZFJDy4=; b=Rk+ydzOwt0QxCYnYiEJOASVSvesDc62yl8AMFqQ6qS1NujyzKM4x/RXT fYlVhn/C9UTGqbAT4vDLloRvI72cVcb3NG2wr1Xtl6dO4XC++Ro8ZMJK8 veApMTP/PmLJTt1Oew3XJatdy4bCDA2bWWHDljeZ1+5FwQcMqqE4WvW2l KlAHv0EaEld6tgq8joWg1eZS/sjh8oExvRnxHMnnD1ImaQrA67QstTn1m 82n9bORcYdzJby4zLzn7PbKi9HJKkAqHpwa5U+V7JfR4MDNzRdXTIypCm Muc29ZIMpLFuCvQNpxY4ChhdGxfnCtbOedke8KEUdSMWWScmHemw+ioQ7 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="309894472" X-IronPort-AV: E=Sophos;i="5.96,152,1665471600"; d="scan'208";a="309894472" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 17:52:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="762099785" X-IronPort-AV: E=Sophos;i="5.96,152,1665471600"; d="scan'208";a="762099785" Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga004.jf.intel.com with ESMTP; 09 Nov 2022 17:52:53 -0800 From: Jiaxi Chen To: kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com, ndesaulniers@google.com, alexandre.belloni@bootlin.com, peterz@infradead.org, jpoimboe@kernel.org, chang.seok.bae@intel.com, pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com, jmattson@google.com, sandipan.das@amd.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, fenghua.yu@intel.com, keescook@chromium.org, nathan@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/7] x86: KVM: Move existing x86 CPUID leaf [CPUID_7_1_EAX] to kvm-only leaf Date: Thu, 10 Nov 2022 09:52:46 +0800 Message-Id: <20221110015252.202566-2-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221110015252.202566-1-jiaxi.chen@linux.intel.com> References: <20221110015252.202566-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" cpuid_leaf[12] CPUID_7_1_EAX has only two bits are in use currently: - AVX-VNNI CPUID.(EAX=3D7,ECX=3D1):EAX[bit 4] - AVX512-BF16 CPUID.(EAX=3D7,ECX=3D1):EAX[bit 5] These two bits have no other kernel usages other than the guest CPUID advertisement in KVM. Given that and to save space for kernel feature bits, move these two bits to the kvm-only subleaves. The existing leaf cpuid_leafs[12] is set to CPUID_LNX_5 so future feature can pick it. This basically reverts: - commit b85a0425d805 ("Enumerate AVX Vector Neural Network instructions") - commit b302e4b176d0 ("x86/cpufeatures: Enumerate the new AVX512 BFLOAT16 instructions") - commit 1085a6b585d7 ("KVM: Expose AVX_VNNI instruction to guset") Signed-off-by: Jiaxi Chen --- arch/x86/include/asm/cpufeature.h | 2 +- arch/x86/include/asm/cpufeatures.h | 4 +--- arch/x86/kernel/cpu/common.c | 6 ------ arch/x86/kernel/cpu/cpuid-deps.c | 1 - arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/reverse_cpuid.h | 5 +++++ 6 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index 1a85e1fb0922..b2905ddd7ab4 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -24,7 +24,7 @@ enum cpuid_leafs CPUID_7_0_EBX, CPUID_D_1_EAX, CPUID_LNX_4, - CPUID_7_1_EAX, + CPUID_LNX_5, CPUID_8000_0008_EBX, CPUID_6_EAX, CPUID_8000_000A_EDX, diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index b71f4f2ecdd5..ec468d6eaf06 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -305,9 +305,7 @@ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ =20 -/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ -#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ -#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +/* Linux-defined mapping, word 12 */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..0c19c84d7ba0 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1026,12 +1026,6 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_capability[CPUID_7_0_EBX] =3D ebx; c->x86_capability[CPUID_7_ECX] =3D ecx; c->x86_capability[CPUID_7_EDX] =3D edx; - - /* Check valid sub-leaf index before accessing it */ - if (eax >=3D 1) { - cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); - c->x86_capability[CPUID_7_1_EAX] =3D eax; - } } =20 /* Extended state features: level 0x0000000d */ diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index c881bcafba7d..a88e0e8c39fa 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -68,7 +68,6 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC }, { X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, - { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA }, diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 7065462378e2..89f5e7f0402b 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -656,7 +656,7 @@ void kvm_set_cpu_caps(void) if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); =20 - kvm_cpu_cap_mask(CPUID_7_1_EAX, + kvm_cpu_cap_init_scattered(CPUID_7_1_EAX, F(AVX_VNNI) | F(AVX512_BF16) ); =20 diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index a19d473d0184..674de5b24f8d 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -13,6 +13,7 @@ */ enum kvm_only_cpuid_leafs { CPUID_12_EAX =3D NCAPINTS, + CPUID_7_1_EAX, NR_KVM_CPU_CAPS, =20 NKVMCAPINTS =3D NR_KVM_CPU_CAPS - NCAPINTS, @@ -24,6 +25,10 @@ enum kvm_only_cpuid_leafs { #define KVM_X86_FEATURE_SGX1 KVM_X86_FEATURE(CPUID_12_EAX, 0) #define KVM_X86_FEATURE_SGX2 KVM_X86_FEATURE(CPUID_12_EAX, 1) =20 +/* Intel-defined sub-features, CPUID level 0x00000007:1 (EAX) */ +#define X86_FEATURE_AVX_VNNI KVM_X86_FEATURE(CPUID_7_1_EAX, 4) +#define X86_FEATURE_AVX512_BF16 KVM_X86_FEATURE(CPUID_7_1_EAX, 5) + struct cpuid_reg { u32 function; u32 index; --=20 2.27.0