From nobody Mon Nov 11 02:24:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A210C4332F for ; Mon, 7 Nov 2022 16:15:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232369AbiKGQPu (ORCPT ); Mon, 7 Nov 2022 11:15:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232338AbiKGQPq (ORCPT ); Mon, 7 Nov 2022 11:15:46 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5AF312737; Mon, 7 Nov 2022 08:15:45 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 49D94ED1; Mon, 7 Nov 2022 08:15:51 -0800 (PST) Received: from pierre123.arm.com (pierre123.nice.arm.com [10.34.100.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D2B393F534; Mon, 7 Nov 2022 08:15:29 -0800 (PST) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Pierre Gondois , Rob Herring , Krzysztof Kozlowski , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , Tsahee Zidenberg , Antoine Tenart , Brijesh Singh , Suravee Suthikulpanit , Tom Lendacky , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Khuong Dinh , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , William Zhang , Anand Gore , Kursad Oney , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Alim Akhtar , Shawn Guo , Li Yang , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Chester Lin , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Matthias Brugger , NXP S32 Linux Team , Wei Xu , Chanho Min , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Lars Povlsen , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Thierry Reding , Jonathan Hunter , Andy Gross , Bjorn Andersson , Konrad Dybcio , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Kunihiko Hayashi , Masami Hiramatsu , Jisheng Zhang , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Viorel Suman , Abel Vesa , Shenwei Wang , Shijie Qin , Ming Qian , Peng Fan , Adam Ford , Lucas Stach , Tim Harvey , Li Jun , Richard Zhu , Joakim Zhang , Markus Niebel , Marek Vasut , Laurent Pinchart , Paul Elder , Alexander Stein , Martin Kepplinger , David Heidelberg , Liu Ying , Oliver Graute , Zhou Peng , Haibo Chen , Ahmad Fatoum , Clark Wang , Jacky Bai , Chris Packham , Vadym Kochan , Sameer Pujar , Prathamesh Shete , Mikko Perttunen , Akhil R , Sumit Gupta , Diogo Ivo , Vidya Sagar , Ashish Mhetre , Johan Jonker , Christopher Obbard , Ezequiel Garcia , Aswani Reddy , Shashank Prashar , Ajay Kumar , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-mediatek@lists.infradead.org, openbmc@lists.ozlabs.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-realtek-soc@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 08/23] arm64: dts: Update cache properties for freescale Date: Mon, 7 Nov 2022 16:57:01 +0100 Message-Id: <20221107155825.1644604-9-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221107155825.1644604-1-pierre.gondois@arm.com> References: <20221107155825.1644604-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 ++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 + arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++ arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++ 16 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls1028a.dtsi index ac1c3a7e5f7a..1b33cabb4e14 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -46,6 +46,7 @@ cpu1: cpu@1 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls1043a.dtsi index 704f72caddd3..b9fd24cdc919 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -84,6 +84,7 @@ cpu3: cpu@3 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls1046a.dtsi index 3d9e29824bb2..a01e3cfec77f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -79,6 +79,7 @@ cpu3: cpu@3 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls2080a.dtsi index a2cadf757148..1e5d76c4d83d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -95,18 +95,22 @@ cpu7: cpu@301 { =20 cluster0_l2: l2-cache0 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 cluster1_l2: l2-cache1 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 cluster2_l2: l2-cache2 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 cluster3_l2: l2-cache3 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls2088a.dtsi index c3dc38188c17..c12c86915ec8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -95,18 +95,22 @@ cpu7: cpu@301 { =20 cluster0_l2: l2-cache0 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 cluster1_l2: l2-cache1 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 cluster2_l2: l2-cache2 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 cluster3_l2: l2-cache3 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-lx2160a.dtsi index 8c76d86cb756..50c19e8405d5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -300,6 +300,7 @@ cpu701: cpu@701 { =20 cluster0_l2: l2-cache0 { compatible =3D "cache"; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; @@ -308,6 +309,7 @@ cluster0_l2: l2-cache0 { =20 cluster1_l2: l2-cache1 { compatible =3D "cache"; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; @@ -316,6 +318,7 @@ cluster1_l2: l2-cache1 { =20 cluster2_l2: l2-cache2 { compatible =3D "cache"; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; @@ -324,6 +327,7 @@ cluster2_l2: l2-cache2 { =20 cluster3_l2: l2-cache3 { compatible =3D "cache"; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; @@ -332,6 +336,7 @@ cluster3_l2: l2-cache3 { =20 cluster4_l2: l2-cache4 { compatible =3D "cache"; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; @@ -340,6 +345,7 @@ cluster4_l2: l2-cache4 { =20 cluster5_l2: l2-cache5 { compatible =3D "cache"; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; @@ -348,6 +354,7 @@ cluster5_l2: l2-cache5 { =20 cluster6_l2: l2-cache6 { compatible =3D "cache"; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; @@ -356,6 +363,7 @@ cluster6_l2: l2-cache6 { =20 cluster7_l2: l2-cache7 { compatible =3D "cache"; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/d= ts/freescale/imx8dxl.dtsi index 5ddbda0b4def..9a7965a694a2 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -59,6 +59,7 @@ A35_1: cpu@1 { =20 A35_L2: l2-cache0 { compatible =3D "cache"; + cache-level =3D <2>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index dabd94dc30c4..149b7af5349d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; cache-size =3D <0x80000>; cache-line-size =3D <64>; cache-sets =3D <512>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index ad0b99adf691..12cc1a6c50c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; cache-size =3D <0x80000>; cache-line-size =3D <64>; cache-sets =3D <512>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index bb916a0948a8..e2a9ddbe4d40 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -123,6 +123,7 @@ A53_3: cpu@3 { =20 A53_L2: l2-cache0 { compatible =3D "cache"; + cache-unified; cache-level =3D <2>; cache-size =3D <0x80000>; cache-line-size =3D <64>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mq.dtsi index 19eaa523564d..1b7e7ac2750a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -179,6 +179,7 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8qm.dtsi index c9c2b6536233..41ce8336f29e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -136,6 +136,7 @@ A72_1: cpu@101 { A53_L2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; @@ -144,6 +145,7 @@ A53_L2: l2-cache0 { A72_L2: l2-cache1 { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; cache-size =3D <0x100000>; cache-line-size =3D <64>; cache-sets =3D <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8qxp.dtsi index f4ea18bb95ab..85c0b1d2bac5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -127,6 +127,7 @@ A35_3: cpu@3 { A35_L2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; cache-size =3D <0x80000>; cache-line-size =3D <64>; cache-sets =3D <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8ulp.dtsi index 06ce5f19aa8a..32193a43ff49 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -51,6 +51,7 @@ A35_1: cpu@1 { =20 A35_L2: l2-cache0 { compatible =3D "cache"; + cache-level =3D <2>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 824d401e7a2c..d8c82da88ca0 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -52,10 +52,12 @@ cpu3: cpu@101 { =20 cluster0_l2: l2-cache0 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 cluster1_l2: l2-cache1 { compatible =3D "cache"; + cache-level =3D <2>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/d= ts/freescale/s32v234.dtsi index ba0b5305d481..3e306218d533 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -61,10 +61,12 @@ cpu3: cpu@101 { =20 cluster0_l2_cache: l2-cache0 { compatible =3D "cache"; + cache-level =3D <2>; }; =20 cluster1_l2_cache: l2-cache1 { compatible =3D "cache"; + cache-level =3D <2>; }; }; =20 --=20 2.25.1