From nobody Tue Apr 16 08:36:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DA57C433FE for ; Mon, 7 Nov 2022 13:02:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232146AbiKGNCV (ORCPT ); Mon, 7 Nov 2022 08:02:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231374AbiKGNCH (ORCPT ); Mon, 7 Nov 2022 08:02:07 -0500 Received: from vps.xff.cz (vps.xff.cz [195.181.215.36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE2EA1C425; Mon, 7 Nov 2022 05:02:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xff.cz; s=mail; t=1667826120; bh=Z5HZQ0FJ5zop6RxxhYVUF6pwXoF1Wmv4094FaI/3RFs=; h=From:To:Cc:Subject:Date:From; b=n8Q020NDFCcVdsopFtB8ts4Gk0wCoh5ew+3NXPQL6DBMcHNBJz8cYvtO4pGdraY8x KRiHiA89QGcLSSNvckYb2RwEmDEa6NwaKMNvBHTOqiLptjOrwZRBiFrlP8itzXuzS8 pmwwV2vKj5YyWNyzSKJZY9tklB8a2fXP6EVLwBLE= From: Ondrej Jirman To: linux-rockchip@lists.infradead.org Cc: Ondrej Jirman , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Michael Riesch , Peter Geis , Sascha Hauer , Nicolas Frattaroli , Frank Wunderlich , Chris Morgan , Ezequiel Garcia , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3] arm64: dts: rockchip: rk356x: Fix PCIe register map and ranges Date: Mon, 7 Nov 2022 14:01:56 +0100 Message-Id: <20221107130157.1425882-1-megi@xff.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" I have two Realtek PCIe wifi cards connected over the 4 port PCIe bridge to Quartz64-A. The cards fail to work, when nvme SSD is connected at the same time to the bridge. Without nvme connected, cards work fine. The issue seems to be related to mixed use of devices which make use of I/O ranges and memory ranges. This patch changes I/O, MEM and config mappings so that these use the 32bit outbound address space at 0xf4000000, and 64bit MEM range uses the whole 0x3_0000_0000 outbound address range. These values were suggested by pgwipeout: https://lore.kernel.org/lkml/875ygbsrf3.fsf@bloch.sibelius.xs4all.nl/T/#m= 84b5f6992cc26dffe0d3783c0d8c9c86e5e10c10 This is identical to how BSP does the mappings. This change to the regs/ranges makes the issue go away and both nvme and wifi cards work when connected at the same time to the bridge. I tested the nvme with large amount of reads/writes, both behind the PCIe bridge and when directly connected to Quartz64-A board. Signed-off-by: Ondrej Jirman --- v3: - changed ranges to the ones suggested by pgwipeout arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts= /rockchip/rk356x.dtsi index 164708f1eb67..726c948ccbf0 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -951,7 +951,8 @@ pcie2x1: pcie@fe260000 { compatible =3D "rockchip,rk3568-pcie"; reg =3D <0x3 0xc0000000 0x0 0x00400000>, <0x0 0xfe260000 0x0 0x00010000>, - <0x3 0x3f000000 0x0 0x01000000>; + <0x0 0xf4000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; interrupts =3D , , @@ -973,15 +974,17 @@ pcie2x1: pcie@fe260000 { <0 0 0 4 &pcie_intc 3>; linux,pci-domain =3D <0>; num-ib-windows =3D <6>; - num-ob-windows =3D <2>; + num-ob-windows =3D <8>; max-link-speed =3D <2>; msi-map =3D <0x0 &gic 0x0 0x1000>; num-lanes =3D <1>; phys =3D <&combphy2 PHY_TYPE_PCIE>; phy-names =3D "pcie-phy"; power-domains =3D <&power RK3568_PD_PIPE>; - ranges =3D <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 - 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; + ranges =3D <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; + resets =3D <&cru SRST_PCIE20_POWERUP>; reset-names =3D "pipe"; #address-cells =3D <3>; --=20 2.38.1