From nobody Thu Apr 9 13:42:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4D43C4167D for ; Mon, 7 Nov 2022 07:15:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231178AbiKGHPX (ORCPT ); Mon, 7 Nov 2022 02:15:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231135AbiKGHPP (ORCPT ); Mon, 7 Nov 2022 02:15:15 -0500 Received: from mail-qv1-xf2b.google.com (mail-qv1-xf2b.google.com [IPv6:2607:f8b0:4864:20::f2b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0315413D13; Sun, 6 Nov 2022 23:15:15 -0800 (PST) Received: by mail-qv1-xf2b.google.com with SMTP id x15so7567265qvp.1; Sun, 06 Nov 2022 23:15:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JTuGs4Qr8OjIPTV0EW+3fOR56dGgW7kE0R2qX2cKw3M=; b=lGzX8P6W7zgpcKY2ylsffT7ItgS2ThQqmOG+9r35EVmd8AMXBLsiGPK6JE/5FQdgvE D71/a3QofCTUTYPSoHE12mcp+HW0ZF0DehozUwvTPMmvlwYXlmGEZ/1qBZ7L0o7i1D9i FFowQIO82vroCPcleeWyOVCYnnlDXKghRhmA2U4QQUBwbH2H0mzzlAPxUB2PgOZ3u5VJ yn5x8ZFKobFI3vVr5j6It5Hu8m6S3+i0iZ/shOGJknfQE5+sosUJ5/zIC0DLJ43X9Lp2 dEXqIMU1kMBMwbBfd1V1ETase9Wf9qx1QKFARiEHAC4cdNPZA8TghoraBmM+D+07hPEd uZsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JTuGs4Qr8OjIPTV0EW+3fOR56dGgW7kE0R2qX2cKw3M=; b=TmT1D3AOUI0a8qXcM2iXDYw94Utw37oJfK7HQPqnoxQCYwL1fFv/KalTJZX2CVIQlY KMRrDCXuGjJnYj/74QlUzl36IM2zNClTev6lM8amAYC2idu0BaDrmOWNjVdaqp7V9A9t sTh59BH74aUcftGgOU12akJE0UhtGnvmahFnHYJ51UUlFyKHV11k0kh06GdNQUEwYlgz VdzPqzps665W7rGJ/zGGvVkvLLXQ/XJxC4iZfS4k7qgxkyzPASRWwoCDojn+vIrcUij+ DI6VGyhdJcV7eiPXSDBrBYr1ai3AkWcHMP2RYuQfDagbW9dZUF6fdi0B41WB1IV02FEv XTnw== X-Gm-Message-State: ACrzQf2MbeFzsmA6Dg09FLvwC055lxphNE7ks96hdK0hH/0lQKYxXD5g ApD+zS23GPy5Ec+eArS3y3Y= X-Google-Smtp-Source: AMsMyM7EMf8qeKS1zjYmLF98QBhhMYd9qMDGQBRAc31DPFEcgLyErj+9GDeMmbDWbhjXCx77hWl0jg== X-Received: by 2002:a0c:8107:0:b0:496:a715:dc8c with SMTP id 7-20020a0c8107000000b00496a715dc8cmr43396491qvc.96.1667805314146; Sun, 06 Nov 2022 23:15:14 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:13 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring Subject: [PATCH v1 1/7] dt-bindings: arm: imx: Add i.MXRT compatible Documentation Date: Mon, 7 Nov 2022 02:15:05 -0500 Message-Id: <20221107071511.2764628-2-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Recently the imxrt1050 was added but the cpu compatible node wasn't added. Add both i.MXRT1170 and 1050 compatibles to fsl.yaml. Cc: Giulio Benetti Signed-off-by: Jesse Taube Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/fsl.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 59e6e8b4dab3..a95b774e5d67 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1046,6 +1046,18 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 =20 + - description: i.MXRT1050 based Boards + items: + - enum: + - fsl,imxrt1050-evk # i.MXRT1050 EVK Board + - const: fsl,imxrt1050 + + - description: i.MXRT1170 based Boards + items: + - enum: + - fsl,imxrt1170-evk # i.MXRT1170 EVK Board + - const: fsl,imxrt1170 + - description: Freescale Vybrid Platform Device Tree Bindings =20 --=20 2.37.2 From nobody Thu Apr 9 13:42:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F129CC433FE for ; Mon, 7 Nov 2022 07:15:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231264AbiKGHP0 (ORCPT ); Mon, 7 Nov 2022 02:15:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231146AbiKGHPR (ORCPT ); Mon, 7 Nov 2022 02:15:17 -0500 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21C0113D13; Sun, 6 Nov 2022 23:15:16 -0800 (PST) Received: by mail-qk1-x72e.google.com with SMTP id g10so6681234qkl.6; Sun, 06 Nov 2022 23:15:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8XNx+rgJgduq7rCvuRhTlcngQGfS0jYPWbvWIVqx1qM=; b=fkfG9ot2ZJgYRbjgmfQajtUOKmevc7ckdcsndCM1TmZAPhW6j+EysoQPGDBwIJRxgq NE3yWYDf/T5yPZRzXdSOGT+vS4p83A0LAfW44V+LJFZgK9HfZBlMxEsYoYeWeMyXy4KR Qneape2Fqn0VRYB72SmDoFFfjTxZNdaDxjcD54Ie9/QNzwfLHy0GVt7fFqgpiWOfVIiO 2/ZnikDSmoABsfIoxJ0p34AQIgAg6jtB3imD0BYedVnBBB1qfS1wnApFT2H7f1Kd0Gti Xqzt60nux9KRPbQAhfoM1GMffCVsXXi2CEJKKCPjXbrYLSbVeV2PowzLNHs5MP37kAl2 UIMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8XNx+rgJgduq7rCvuRhTlcngQGfS0jYPWbvWIVqx1qM=; b=ie7sg38fc+QZo7klBrQEAgQaFAQz6opW2NGnKb4Q89NabrPOLlHMaEJlE3ndDsKFjN aXF/IZvEOIWFMtLj1mY66RxetuoReWfy8fS7qDaSA45QXcxOYXwhbImcAso1H5JUlgLi rVB4O7G7+dJUj5WV54LqTWY0bpaUuRz7gtBhQxJOIZP3Wuixb+5sU0icGeUmOfIXBzo+ 3QBYC+qu+03usCR0vD7Hwq+jeIimoYfftWC9WbTCR2/x9N0uqC/Amni3gEAwNyNw1UVD 3k7fMHO6OFPoQGm/Zgj5nAYBGHG3v/x5Rtyrwx3VWirjRWYwiSi/dtoDFTAvu8Lsmv99 lNXg== X-Gm-Message-State: ACrzQf27dUlypD50525aRbXObid7qN5Qi8THERjnRBMdnSWrTWdm3D9C aQiLjeeqZUR4xnVT/xo++nI= X-Google-Smtp-Source: AMsMyM77e+VuZnZM7E7UgYqBiy6cpufDm9treTU+akYNQtE5dR3s7GTF4Q0lLO9teekpOEtECVAWow== X-Received: by 2002:a05:620a:2b45:b0:6fa:509f:d0c2 with SMTP id dp5-20020a05620a2b4500b006fa509fd0c2mr21882138qkb.302.1667805315213; Sun, 06 Nov 2022 23:15:15 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:14 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v1 2/7] dt-bindings: pinctrl: Fix file path for pinfunc include Date: Mon, 7 Nov 2022 02:15:06 -0500 Message-Id: <20221107071511.2764628-3-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Reference to pinfunc.h was wrong. Fix it. Cc: Giulio Benetti Signed-off-by: Jesse Taube --- Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b= /Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml index 1278f7293560..db5fe66ad873 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml @@ -35,7 +35,7 @@ patternProperties: each entry consists of 6 integers and represents the mux and con= fig setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, whic= h can - be found in . The = last + be found in . The last integer CONFIG is the pad setting value like pull-up on this pin= . Please refer to i.MXRT1050 Reference Manual for detailed CONFIG setting= s. $ref: /schemas/types.yaml#/definitions/uint32-matrix --=20 2.37.2 From nobody Thu Apr 9 13:42:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEDB4C07E9D for ; Mon, 7 Nov 2022 07:15:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231400AbiKGHPj (ORCPT ); Mon, 7 Nov 2022 02:15:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231211AbiKGHPU (ORCPT ); Mon, 7 Nov 2022 02:15:20 -0500 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5501513D3F; Sun, 6 Nov 2022 23:15:17 -0800 (PST) Received: by mail-qv1-xf30.google.com with SMTP id i12so7555431qvs.2; Sun, 06 Nov 2022 23:15:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rujbv6bKgQOEyHFPYldtrR7Cpoq25BGO11nL2f1oX38=; b=iSLvidCkZqtoV2Tl9IDn05Yg1hwAwzWvcwIQeK0ZGCShauUXjF5rgGeEORYUiFhhnB cLOmsGvH388K/cokMP6/QjxfakJbvxydeqYSe6SsWhZ8l1bzmB9SbaiRk5J8iF+1CLXW tW0a0bOuFM1VUyfJIYPC3tLdNssLw3phjq62I6MuKDwCZNhq0EYk6rwiewoxoluBBScq tQsju5Z/c+6BMLtPIXMGiMD2LLWFaV+P3NtdWmcirSFtxYof35CNGmN6CaBXt5YVmNLC qJLO6Rsbdqop1rw7cwM4ZCnvzQVmxyLnVtIKXWccwRiw05E9L+riGL9QrPnh6+tWkEG5 b8ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rujbv6bKgQOEyHFPYldtrR7Cpoq25BGO11nL2f1oX38=; b=uwKqv4zliM2o17TXwuxjdbfRZ4KBsS3DK/P+Na+PKAKDMAigIMiCu0Nt0tREZPgKs+ ZyUPHL2G9+QjB/Qus06k0oYGj920VbxPzSl/jyk+Ei1Ku59QY5GGuN1jlJDL8UyLlRHp 4hJFdnCjWzvG0SrQRTSROJnfpyTeblJUMG8zvO7mer/E8TmVeptUPVA0OWJYKIkhYojf LxcuemBDGOps4uroKey+gnxvC0SP3CNipMhB+E9HpLtKeMfUs8jr8AuTcEwDsxPxbp1E PCygaMQQBOPjCpfvCrhhBIS35CFb3RGVbCHAsafOsR1OA6BRmFu2XMXxpF7Bn+kS9LH/ N40g== X-Gm-Message-State: ACrzQf0nhW02ourOmEVUykHC6kbu/AYwsf/HsTRe07R1ry5xjcVTYZzd zCqRDjhO7mEbvY523g8kxc4= X-Google-Smtp-Source: AMsMyM6KsjhgOm4uFsTfXn9s49un2+OpakxWD2QhahyM3daQtCGIEYlmtawlYkVmQj+Da5+ugT01Xg== X-Received: by 2002:a05:6214:5015:b0:4bb:5ce1:88c0 with SMTP id jo21-20020a056214501500b004bb5ce188c0mr42492042qvb.15.1667805316339; Sun, 06 Nov 2022 23:15:16 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:16 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v1 3/7] dt-bindings: timer: gpt: Add i.MXRT compatible Documentation Date: Mon, 7 Nov 2022 02:15:07 -0500 Message-Id: <20221107071511.2764628-4-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Both the i.MXRT1170 and 1050 have the same GPT timer as "fsl,imx6dl-gpt" Add i.MXRT to the compatible list. Cc: Giulio Benetti Signed-off-by: Jesse Taube Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Docu= mentation/devicetree/bindings/timer/fsl,imxgpt.yaml index a4f51f46b7a1..716c6afcca1f 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml @@ -31,6 +31,8 @@ properties: - enum: - fsl,imx6sl-gpt - fsl,imx6sx-gpt + - fsl,imxrt1050-gpt + - fsl,imxrt1170-gpt - const: fsl,imx6dl-gpt =20 reg: --=20 2.37.2 From nobody Thu Apr 9 13:42:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5841C43217 for ; Mon, 7 Nov 2022 07:15:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231179AbiKGHPr (ORCPT ); Mon, 7 Nov 2022 02:15:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231161AbiKGHP1 (ORCPT ); Mon, 7 Nov 2022 02:15:27 -0500 Received: from mail-qt1-x832.google.com (mail-qt1-x832.google.com [IPv6:2607:f8b0:4864:20::832]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5459913D43; Sun, 6 Nov 2022 23:15:18 -0800 (PST) Received: by mail-qt1-x832.google.com with SMTP id c15so6424967qtw.8; Sun, 06 Nov 2022 23:15:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FevbBLdguXCFmnA0gYiJMt8h51HW7EHdkkwF3DmVtiM=; b=Oj0vqp+43Yq+/jWzQLRnuJhR+XUgWDl31H1CMGjjWKzn9r8KSbLXPNTvPdJEaZ5LZI q0MoSips3u+fpLOOMflvcjpjvyHYCYof38b3K4RFWeTtVCT7vOqgzTstARhu2SGwZ5eN RbfQACddReC7PUwmkvuMRr6z3s8M2BHVvamSCwAp+KQV6AKPJDYvBMPGskowB03uihae DCxz4EXPbPSz3mxqN8S7a+Egc602hA2cYKRn/cia5q81vyKYiIQ0CIzpEgbpQaAM3j7e nf6rKB1Rvpgv2X1vmH/u3iSF/JcwAOHP58jjUrs0TKhaG8DPnACLEyb9VSIJt2HrqZ04 5Atw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FevbBLdguXCFmnA0gYiJMt8h51HW7EHdkkwF3DmVtiM=; b=jM+/D7I9q6aFOaM8uZlWXkPtloGyo9XxF9lsRFQFh0CIWDnNUe0MAkJiv/59k6WtgY edW7JjLvvtwiQ6ULPXehAEJ7PLC+RGIXDG38Jo/tg4wcoi42WubhW1lfG8D6vxUsgS8F gWHY1fOzWq/I6ts+WG4RVHK3wS5BVJwK1129q0fGjDXoCEpaHqyrIq9Pndap2qz78Kaw swKde++1oacE8MLjJqTmoElOHuv5X/wV5Bow1sJgClC/aP5tDw97jkTvNgjhA1xJDFNk fof3oWC4pFencz34sEGiUtg4vxOa9lcQr46Cx3Dp07vCNm6jV2fYTr479mK6YZ+QXzN0 jCKQ== X-Gm-Message-State: ANoB5pkKnsMY4is+q9ZVsKo16W0zB9yzGfXCyA5xkBx9yRDJX2u97smo hQbU5Vud0vq7gWcpfsv7sbI= X-Google-Smtp-Source: AA0mqf7SQASvWKnqHMl5xXSgn1OAMYbUQcQ7wyKnX1Z91mCBgs4y4/2sjwK3qPE81S9M9O3kpXEbRQ== X-Received: by 2002:a05:622a:11d0:b0:3a5:8ff2:8496 with SMTP id n16-20020a05622a11d000b003a58ff28496mr2679067qtk.302.1667805317449; Sun, 06 Nov 2022 23:15:17 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:17 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring Subject: [PATCH v1 4/7] dt-bindings: serial: fsl-lpuart: add i.MXRT1170 compatible Date: Mon, 7 Nov 2022 02:15:08 -0500 Message-Id: <20221107071511.2764628-5-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add i.MXRT1170 compatible string to Documentation. Cc: Giulio Benetti Signed-off-by: Jesse Taube Acked-by: Rob Herring --- Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Doc= umentation/devicetree/bindings/serial/fsl-lpuart.yaml index 30eaa62e1aed..74f75f669e77 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -32,6 +32,9 @@ properties: - fsl,imx8qm-lpuart - fsl,imx8dxl-lpuart - const: fsl,imx8qxp-lpuart + - items: + - const: fsl,imxrt1050-lpuart + - const: fsl,imxrt1170-lpuart =20 reg: maxItems: 1 --=20 2.37.2 From nobody Thu Apr 9 13:42:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AE75C43219 for ; Mon, 7 Nov 2022 07:16:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231436AbiKGHQM (ORCPT ); Mon, 7 Nov 2022 02:16:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231311AbiKGHPg (ORCPT ); Mon, 7 Nov 2022 02:15:36 -0500 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24D7313D62; Sun, 6 Nov 2022 23:15:20 -0800 (PST) Received: by mail-qk1-x72e.google.com with SMTP id k4so6680943qkj.8; Sun, 06 Nov 2022 23:15:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h0r57Vvw4A7lJzIo/9EbiUI/3USItkedCC8EGqi95SU=; b=FmYBOZqYub8si8sSull+j9QRtiVf7LQKFWqcrUoqWpAz/CjcJmAbFmKbUQiUB2HMya WLVc8I+SP19VDoZZ5exD/CvkLgRcuX23bE5NRaTfJG7NVFjXGZJes0VeqCxZ4SICr+lQ Q9kG0U5bueB+d1T7hNWtWMtsvDin8p1Jn5Q0ubf8ClzFXepOumhs3uQ1qjDzZRWEt1V6 JVe4uyeZlx/NVfW3hQmRl+MkAdMQq21aqyAXbKbxcob1LcMUZ+8mVyfwM5ChBuCO+Dql ILziT+Pvc/mUADH/AcTg5Db7KY395ykiVuNRr7vvdFyBFx+5VjJd/YXBoT5wUx/E35eU qbqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h0r57Vvw4A7lJzIo/9EbiUI/3USItkedCC8EGqi95SU=; b=6Uz07WngoOhQ3m5FXKe2V5oawvJC6iumzlwOG/hapW+d2wD5Ut7EgLIute7HBVUtcr +K3Rv3YOm5S1mZZra0nMlXZS98x3iBVHSXYiZ0nyTfgCbcUjOCeTYrkI/VeePwJJmw6P 8mgVbA1iEzspO2kAwKt4e6TTZSluxrfWWhDXe/OjZZvsF1JKdvDcncHhVsbUK22GmrL/ Etvquus0UM4ovcQTJ3S60bgQpOZP7TKEyvVCk7iwufbjDPTkfTlGNXA1/bWys+9YbADW YZ7x748artRJPoKYmTfu9yNIv6krgTFHtx2Q5f/Y6vAgbgEB/8uVUQy0DnSUi1RxOfpG KsUA== X-Gm-Message-State: ACrzQf0PrA+ZGcWiw6T9qDjoMxB7JAMERSLgywd80iTpmxtL0h1sbMPS uOmpzT0sKnvC7FutK+uQ7aU= X-Google-Smtp-Source: AMsMyM4Cger4O1dNqIMvlSZOE1rmt3mv+pZVh6V5xEukOqvLnKxxpug2f51xjjbdOYp+fpY6Jbtzcw== X-Received: by 2002:a05:620a:9cb:b0:6fa:22bf:9fa with SMTP id y11-20020a05620a09cb00b006fa22bf09famr30741111qky.625.1667805319141; Sun, 06 Nov 2022 23:15:19 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:18 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring Subject: [PATCH v1 5/7] dt-bindings: mmc: fsl-imx-esdhc: add i.MXRT1170 compatible Date: Mon, 7 Nov 2022 02:15:09 -0500 Message-Id: <20221107071511.2764628-6-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add i.MXRT1170 compatible string to Documentation. Cc: Giulio Benetti Signed-off-by: Jesse Taube Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Doc= umentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml index 29339d0196ec..0e7833478869 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml @@ -75,6 +75,10 @@ properties: - const: fsl,imx8qxp-usdhc - const: fsl,imx7d-usdhc deprecated: true + - items: + - enum: + - fsl,imxrt1170-usdhc + - const: fsl,imxrt1050-usdhc =20 reg: maxItems: 1 --=20 2.37.2 From nobody Thu Apr 9 13:42:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76B29C433FE for ; Mon, 7 Nov 2022 07:16:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231317AbiKGHP7 (ORCPT ); Mon, 7 Nov 2022 02:15:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231314AbiKGHPg (ORCPT ); Mon, 7 Nov 2022 02:15:36 -0500 Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A54E13D71; Sun, 6 Nov 2022 23:15:21 -0800 (PST) Received: by mail-qv1-xf31.google.com with SMTP id ml12so7574202qvb.0; Sun, 06 Nov 2022 23:15:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rX9oq4gzaxqNQxYOSZWc5oRwei2M0k3tGKlh2M3xFwY=; b=nXubkkCNVy4EbvJWJwlGX52yAVpSvJfugoUK65TWlb9kHAah9rt/Czzhyy+xGyacY6 Nm5jjZ3o7WYsuNlg/NEJVn0Jt6RDvQbI4h9kE7QYwPpd3GdMSqAPbqnnj2ELOqIZfziv qmsrtZ5IzPItyA+BBfhITZbS9TNdKNbvl3OO47g7/nXujavFl7kq7z3MdMLliYT52T+h h4+7dsLzlFcKldjT10mX2NwxCQl/UmSwDIa9F5rAVReZBjVF6AbCyPQ7V63fKFGYGb7p R9i7/lWgs3NamZ4nh8rLhRjaDpblu+od2hc8QmKJBWBp5H4nHBh95HPAB2dmkSOwXkbK 2sZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rX9oq4gzaxqNQxYOSZWc5oRwei2M0k3tGKlh2M3xFwY=; b=qzkrSfor+QzFG3haL0wWqVTcS5U1UmZULnx+2pnIXW1fazSS/Pwpuko0P6tn7ot23V Hb4pabbvzcJ34UX9rjYv0gCKlHU1K21zCmUo/108V+5konMNtJRh14QYT6CgeO+mecwo h+UEndI1Gp8wglZF1QuFytKHEpseky49kLEROssdcRLLgwx+A/6o3m4+erKK/0Bz80mA BvK5fqn+DUQsrD6ZWfnTPfTDEKxcL2UuhTIrwhsargnQDap8ivsfxaRq+5gZWEtHaZ8v RAlVW3/vbfEsayfg6Ofu0asPDnoqScmISWfaK2wudAFP34+UpQSjAbUs0Nqv7vyP6DO4 oelw== X-Gm-Message-State: ACrzQf1Xcak5cS+rOCWI/oSrQ0XOsceky2csl/5pacRW5nOU0GAYi0TC tXQeSigf7zHcSqVQ3PAHB2M= X-Google-Smtp-Source: AMsMyM75UWsLtkNX29wLm6t+PvP+g8F6i0ThbS1ahxlr4tDFGa2Q84ZiHgouH3LyD3hwtnVsryBb4Q== X-Received: by 2002:a05:6214:29e9:b0:4bc:da6:d604 with SMTP id jv9-20020a05621429e900b004bc0da6d604mr32888792qvb.106.1667805320233; Sun, 06 Nov 2022 23:15:20 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:19 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v1 6/7] pinctrl: freescale: Fix i.MXRT1050 pad names Date: Mon, 7 Nov 2022 02:15:10 -0500 Message-Id: <20221107071511.2764628-7-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The pad names for the i.MXRT1050 were incorrect. Fix them. Cc: Giulio Benetti Signed-off-by: Jesse Taube --- drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 546 ++++++++---------- 1 file changed, 253 insertions(+), 293 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctr= l/freescale/pinctrl-imxrt1050.c index 11f31c90ad30..def683839ebe 100644 --- a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c @@ -13,155 +13,135 @@ #include "pinctrl-imx.h" =20 enum imxrt1050_pads { - IMXRT1050_PAD_RESERVE0 =3D 0, - IMXRT1050_PAD_RESERVE1 =3D 1, - IMXRT1050_PAD_RESERVE2 =3D 2, - IMXRT1050_PAD_RESERVE3 =3D 3, - IMXRT1050_PAD_RESERVE4 =3D 4, - IMXRT1050_PAD_RESERVE5 =3D 5, - IMXRT1050_PAD_RESERVE6 =3D 6, - IMXRT1050_PAD_RESERVE7 =3D 7, - IMXRT1050_PAD_RESERVE8 =3D 8, - IMXRT1050_PAD_RESERVE9 =3D 9, - IMXRT1050_IOMUXC_GPIO1_IO00 =3D 10, - IMXRT1050_IOMUXC_GPIO1_IO01 =3D 11, - IMXRT1050_IOMUXC_GPIO1_IO02 =3D 12, - IMXRT1050_IOMUXC_GPIO1_IO03 =3D 13, - IMXRT1050_IOMUXC_GPIO1_IO04 =3D 14, - IMXRT1050_IOMUXC_GPIO1_IO05 =3D 15, - IMXRT1050_IOMUXC_GPIO1_IO06 =3D 16, - IMXRT1050_IOMUXC_GPIO1_IO07 =3D 17, - IMXRT1050_IOMUXC_GPIO1_IO08 =3D 18, - IMXRT1050_IOMUXC_GPIO1_IO09 =3D 19, - IMXRT1050_IOMUXC_GPIO1_IO10 =3D 20, - IMXRT1050_IOMUXC_GPIO1_IO11 =3D 21, - IMXRT1050_IOMUXC_GPIO1_IO12 =3D 22, - IMXRT1050_IOMUXC_GPIO1_IO13 =3D 23, - IMXRT1050_IOMUXC_GPIO1_IO14 =3D 24, - IMXRT1050_IOMUXC_GPIO1_IO15 =3D 25, - IMXRT1050_IOMUXC_ENET_MDC =3D 26, - IMXRT1050_IOMUXC_ENET_MDIO =3D 27, - IMXRT1050_IOMUXC_ENET_TD3 =3D 28, - IMXRT1050_IOMUXC_ENET_TD2 =3D 29, - IMXRT1050_IOMUXC_ENET_TD1 =3D 30, - IMXRT1050_IOMUXC_ENET_TD0 =3D 31, - IMXRT1050_IOMUXC_ENET_TX_CTL =3D 32, - IMXRT1050_IOMUXC_ENET_TXC =3D 33, - IMXRT1050_IOMUXC_ENET_RX_CTL =3D 34, - IMXRT1050_IOMUXC_ENET_RXC =3D 35, - IMXRT1050_IOMUXC_ENET_RD0 =3D 36, - IMXRT1050_IOMUXC_ENET_RD1 =3D 37, - IMXRT1050_IOMUXC_ENET_RD2 =3D 38, - IMXRT1050_IOMUXC_ENET_RD3 =3D 39, - IMXRT1050_IOMUXC_SD1_CLK =3D 40, - IMXRT1050_IOMUXC_SD1_CMD =3D 41, - IMXRT1050_IOMUXC_SD1_DATA0 =3D 42, - IMXRT1050_IOMUXC_SD1_DATA1 =3D 43, - IMXRT1050_IOMUXC_SD1_DATA2 =3D 44, - IMXRT1050_IOMUXC_SD1_DATA3 =3D 45, - IMXRT1050_IOMUXC_SD1_DATA4 =3D 46, - IMXRT1050_IOMUXC_SD1_DATA5 =3D 47, - IMXRT1050_IOMUXC_SD1_DATA6 =3D 48, - IMXRT1050_IOMUXC_SD1_DATA7 =3D 49, - IMXRT1050_IOMUXC_SD1_RESET_B =3D 50, - IMXRT1050_IOMUXC_SD1_STROBE =3D 51, - IMXRT1050_IOMUXC_SD2_CD_B =3D 52, - IMXRT1050_IOMUXC_SD2_CLK =3D 53, - IMXRT1050_IOMUXC_SD2_CMD =3D 54, - IMXRT1050_IOMUXC_SD2_DATA0 =3D 55, - IMXRT1050_IOMUXC_SD2_DATA1 =3D 56, - IMXRT1050_IOMUXC_SD2_DATA2 =3D 57, - IMXRT1050_IOMUXC_SD2_DATA3 =3D 58, - IMXRT1050_IOMUXC_SD2_RESET_B =3D 59, - IMXRT1050_IOMUXC_SD2_WP =3D 60, - IMXRT1050_IOMUXC_NAND_ALE =3D 61, - IMXRT1050_IOMUXC_NAND_CE0 =3D 62, - IMXRT1050_IOMUXC_NAND_CE1 =3D 63, - IMXRT1050_IOMUXC_NAND_CE2 =3D 64, - IMXRT1050_IOMUXC_NAND_CE3 =3D 65, - IMXRT1050_IOMUXC_NAND_CLE =3D 66, - IMXRT1050_IOMUXC_NAND_DATA00 =3D 67, - IMXRT1050_IOMUXC_NAND_DATA01 =3D 68, - IMXRT1050_IOMUXC_NAND_DATA02 =3D 69, - IMXRT1050_IOMUXC_NAND_DATA03 =3D 70, - IMXRT1050_IOMUXC_NAND_DATA04 =3D 71, - IMXRT1050_IOMUXC_NAND_DATA05 =3D 72, - IMXRT1050_IOMUXC_NAND_DATA06 =3D 73, - IMXRT1050_IOMUXC_NAND_DATA07 =3D 74, - IMXRT1050_IOMUXC_NAND_DQS =3D 75, - IMXRT1050_IOMUXC_NAND_RE_B =3D 76, - IMXRT1050_IOMUXC_NAND_READY_B =3D 77, - IMXRT1050_IOMUXC_NAND_WE_B =3D 78, - IMXRT1050_IOMUXC_NAND_WP_B =3D 79, - IMXRT1050_IOMUXC_SAI5_RXFS =3D 80, - IMXRT1050_IOMUXC_SAI5_RXC =3D 81, - IMXRT1050_IOMUXC_SAI5_RXD0 =3D 82, - IMXRT1050_IOMUXC_SAI5_RXD1 =3D 83, - IMXRT1050_IOMUXC_SAI5_RXD2 =3D 84, - IMXRT1050_IOMUXC_SAI5_RXD3 =3D 85, - IMXRT1050_IOMUXC_SAI5_MCLK =3D 86, - IMXRT1050_IOMUXC_SAI1_RXFS =3D 87, - IMXRT1050_IOMUXC_SAI1_RXC =3D 88, - IMXRT1050_IOMUXC_SAI1_RXD0 =3D 89, - IMXRT1050_IOMUXC_SAI1_RXD1 =3D 90, - IMXRT1050_IOMUXC_SAI1_RXD2 =3D 91, - IMXRT1050_IOMUXC_SAI1_RXD3 =3D 92, - IMXRT1050_IOMUXC_SAI1_RXD4 =3D 93, - IMXRT1050_IOMUXC_SAI1_RXD5 =3D 94, - IMXRT1050_IOMUXC_SAI1_RXD6 =3D 95, - IMXRT1050_IOMUXC_SAI1_RXD7 =3D 96, - IMXRT1050_IOMUXC_SAI1_TXFS =3D 97, - IMXRT1050_IOMUXC_SAI1_TXC =3D 98, - IMXRT1050_IOMUXC_SAI1_TXD0 =3D 99, - IMXRT1050_IOMUXC_SAI1_TXD1 =3D 100, - IMXRT1050_IOMUXC_SAI1_TXD2 =3D 101, - IMXRT1050_IOMUXC_SAI1_TXD3 =3D 102, - IMXRT1050_IOMUXC_SAI1_TXD4 =3D 103, - IMXRT1050_IOMUXC_SAI1_TXD5 =3D 104, - IMXRT1050_IOMUXC_SAI1_TXD6 =3D 105, - IMXRT1050_IOMUXC_SAI1_TXD7 =3D 106, - IMXRT1050_IOMUXC_SAI1_MCLK =3D 107, - IMXRT1050_IOMUXC_SAI2_RXFS =3D 108, - IMXRT1050_IOMUXC_SAI2_RXC =3D 109, - IMXRT1050_IOMUXC_SAI2_RXD0 =3D 110, - IMXRT1050_IOMUXC_SAI2_TXFS =3D 111, - IMXRT1050_IOMUXC_SAI2_TXC =3D 112, - IMXRT1050_IOMUXC_SAI2_TXD0 =3D 113, - IMXRT1050_IOMUXC_SAI2_MCLK =3D 114, - IMXRT1050_IOMUXC_SAI3_RXFS =3D 115, - IMXRT1050_IOMUXC_SAI3_RXC =3D 116, - IMXRT1050_IOMUXC_SAI3_RXD =3D 117, - IMXRT1050_IOMUXC_SAI3_TXFS =3D 118, - IMXRT1050_IOMUXC_SAI3_TXC =3D 119, - IMXRT1050_IOMUXC_SAI3_TXD =3D 120, - IMXRT1050_IOMUXC_SAI3_MCLK =3D 121, - IMXRT1050_IOMUXC_SPDIF_TX =3D 122, - IMXRT1050_IOMUXC_SPDIF_RX =3D 123, - IMXRT1050_IOMUXC_SPDIF_EXT_CLK =3D 124, - IMXRT1050_IOMUXC_ECSPI1_SCLK =3D 125, - IMXRT1050_IOMUXC_ECSPI1_MOSI =3D 126, - IMXRT1050_IOMUXC_ECSPI1_MISO =3D 127, - IMXRT1050_IOMUXC_ECSPI1_SS0 =3D 128, - IMXRT1050_IOMUXC_ECSPI2_SCLK =3D 129, - IMXRT1050_IOMUXC_ECSPI2_MOSI =3D 130, - IMXRT1050_IOMUXC_ECSPI2_MISO =3D 131, - IMXRT1050_IOMUXC_ECSPI2_SS0 =3D 132, - IMXRT1050_IOMUXC_I2C1_SCL =3D 133, - IMXRT1050_IOMUXC_I2C1_SDA =3D 134, - IMXRT1050_IOMUXC_I2C2_SCL =3D 135, - IMXRT1050_IOMUXC_I2C2_SDA =3D 136, - IMXRT1050_IOMUXC_I2C3_SCL =3D 137, - IMXRT1050_IOMUXC_I2C3_SDA =3D 138, - IMXRT1050_IOMUXC_I2C4_SCL =3D 139, - IMXRT1050_IOMUXC_I2C4_SDA =3D 140, - IMXRT1050_IOMUXC_UART1_RXD =3D 141, - IMXRT1050_IOMUXC_UART1_TXD =3D 142, - IMXRT1050_IOMUXC_UART2_RXD =3D 143, - IMXRT1050_IOMUXC_UART2_TXD =3D 144, - IMXRT1050_IOMUXC_UART3_RXD =3D 145, - IMXRT1050_IOMUXC_UART3_TXD =3D 146, - IMXRT1050_IOMUXC_UART4_RXD =3D 147, - IMXRT1050_IOMUXC_UART4_TXD =3D 148, + IMXRT1050_PAD_RESERVE0, + IMXRT1050_PAD_RESERVE1, + IMXRT1050_PAD_RESERVE2, + IMXRT1050_PAD_RESERVE3, + IMXRT1050_PAD_RESERVE4, + IMXRT1050_PAD_EMC_00, + IMXRT1050_PAD_EMC_01, + IMXRT1050_PAD_EMC_02, + IMXRT1050_PAD_EMC_03, + IMXRT1050_PAD_EMC_04, + IMXRT1050_PAD_EMC_05, + IMXRT1050_PAD_EMC_06, + IMXRT1050_PAD_EMC_07, + IMXRT1050_PAD_EMC_08, + IMXRT1050_PAD_EMC_09, + IMXRT1050_PAD_EMC_10, + IMXRT1050_PAD_EMC_11, + IMXRT1050_PAD_EMC_12, + IMXRT1050_PAD_EMC_13, + IMXRT1050_PAD_EMC_14, + IMXRT1050_PAD_EMC_15, + IMXRT1050_PAD_EMC_16, + IMXRT1050_PAD_EMC_17, + IMXRT1050_PAD_EMC_18, + IMXRT1050_PAD_EMC_19, + IMXRT1050_PAD_EMC_20, + IMXRT1050_PAD_EMC_21, + IMXRT1050_PAD_EMC_22, + IMXRT1050_PAD_EMC_23, + IMXRT1050_PAD_EMC_24, + IMXRT1050_PAD_EMC_25, + IMXRT1050_PAD_EMC_26, + IMXRT1050_PAD_EMC_27, + IMXRT1050_PAD_EMC_28, + IMXRT1050_PAD_EMC_29, + IMXRT1050_PAD_EMC_30, + IMXRT1050_PAD_EMC_31, + IMXRT1050_PAD_EMC_32, + IMXRT1050_PAD_EMC_33, + IMXRT1050_PAD_EMC_34, + IMXRT1050_PAD_EMC_35, + IMXRT1050_PAD_EMC_36, + IMXRT1050_PAD_EMC_37, + IMXRT1050_PAD_EMC_38, + IMXRT1050_PAD_EMC_39, + IMXRT1050_PAD_EMC_40, + IMXRT1050_PAD_EMC_41, + IMXRT1050_PAD_AD_B0_00, + IMXRT1050_PAD_AD_B0_01, + IMXRT1050_PAD_AD_B0_02, + IMXRT1050_PAD_AD_B0_03, + IMXRT1050_PAD_AD_B0_04, + IMXRT1050_PAD_AD_B0_05, + IMXRT1050_PAD_AD_B0_06, + IMXRT1050_PAD_AD_B0_07, + IMXRT1050_PAD_AD_B0_08, + IMXRT1050_PAD_AD_B0_09, + IMXRT1050_PAD_AD_B0_10, + IMXRT1050_PAD_AD_B0_11, + IMXRT1050_PAD_AD_B0_12, + IMXRT1050_PAD_AD_B0_13, + IMXRT1050_PAD_AD_B0_14, + IMXRT1050_PAD_AD_B0_15, + IMXRT1050_PAD_AD_B1_00, + IMXRT1050_PAD_AD_B1_01, + IMXRT1050_PAD_AD_B1_02, + IMXRT1050_PAD_AD_B1_03, + IMXRT1050_PAD_AD_B1_04, + IMXRT1050_PAD_AD_B1_05, + IMXRT1050_PAD_AD_B1_06, + IMXRT1050_PAD_AD_B1_07, + IMXRT1050_PAD_AD_B1_08, + IMXRT1050_PAD_AD_B1_09, + IMXRT1050_PAD_AD_B1_10, + IMXRT1050_PAD_AD_B1_11, + IMXRT1050_PAD_AD_B1_12, + IMXRT1050_PAD_AD_B1_13, + IMXRT1050_PAD_AD_B1_14, + IMXRT1050_PAD_AD_B1_15, + IMXRT1050_PAD_B0_00, + IMXRT1050_PAD_B0_01, + IMXRT1050_PAD_B0_02, + IMXRT1050_PAD_B0_03, + IMXRT1050_PAD_B0_04, + IMXRT1050_PAD_B0_05, + IMXRT1050_PAD_B0_06, + IMXRT1050_PAD_B0_07, + IMXRT1050_PAD_B0_08, + IMXRT1050_PAD_B0_09, + IMXRT1050_PAD_B0_10, + IMXRT1050_PAD_B0_11, + IMXRT1050_PAD_B0_12, + IMXRT1050_PAD_B0_13, + IMXRT1050_PAD_B0_14, + IMXRT1050_PAD_B0_15, + IMXRT1050_PAD_B1_00, + IMXRT1050_PAD_B1_01, + IMXRT1050_PAD_B1_02, + IMXRT1050_PAD_B1_03, + IMXRT1050_PAD_B1_04, + IMXRT1050_PAD_B1_05, + IMXRT1050_PAD_B1_06, + IMXRT1050_PAD_B1_07, + IMXRT1050_PAD_B1_08, + IMXRT1050_PAD_B1_09, + IMXRT1050_PAD_B1_10, + IMXRT1050_PAD_B1_11, + IMXRT1050_PAD_B1_12, + IMXRT1050_PAD_B1_13, + IMXRT1050_PAD_B1_14, + IMXRT1050_PAD_B1_15, + IMXRT1050_PAD_SD_B0_00, + IMXRT1050_PAD_SD_B0_01, + IMXRT1050_PAD_SD_B0_02, + IMXRT1050_PAD_SD_B0_03, + IMXRT1050_PAD_SD_B0_04, + IMXRT1050_PAD_SD_B0_05, + IMXRT1050_PAD_SD_B1_00, + IMXRT1050_PAD_SD_B1_01, + IMXRT1050_PAD_SD_B1_02, + IMXRT1050_PAD_SD_B1_03, + IMXRT1050_PAD_SD_B1_04, + IMXRT1050_PAD_SD_B1_05, + IMXRT1050_PAD_SD_B1_06, + IMXRT1050_PAD_SD_B1_07, + IMXRT1050_PAD_SD_B1_08, + IMXRT1050_PAD_SD_B1_09, + IMXRT1050_PAD_SD_B1_10, + IMXRT1050_PAD_SD_B1_11, }; =20 /* Pad names for the pinmux subsystem */ @@ -171,150 +151,130 @@ static const struct pinctrl_pin_desc imxrt1050_pinc= trl_pads[] =3D { IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2), IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3), IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE5), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE6), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE7), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE8), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE9), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO00), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO01), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO02), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO03), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO04), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO05), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO06), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO07), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO08), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO09), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO10), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO11), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO12), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO13), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO14), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO15), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDIO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TX_CTL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RX_CTL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CMD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_RESET_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_STROBE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CD_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CMD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_RESET_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_WP), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_ALE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CLE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA00), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA01), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA02), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA03), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA04), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA05), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA06), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA07), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DQS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_RE_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_READY_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WE_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WP_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_TX), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_RX), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_EXT_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MOSI), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MISO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SS0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MOSI), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MISO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SS0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_TXD), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_16), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_17), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_18), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_19), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_20), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_21), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_22), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_23), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_24), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_25), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_26), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_27), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_28), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_29), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_30), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_31), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_32), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_33), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_34), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_35), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_36), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_37), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_38), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_39), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_40), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_41), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_11), }; =20 static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info =3D { --=20 2.37.2 From nobody Thu Apr 9 13:42:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BA36C433FE for ; Mon, 7 Nov 2022 07:16:27 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[108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:21 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v1 7/7] ARM: dts: imx: Update i.MXRT1050.dtsi compatibles Date: Mon, 7 Nov 2022 02:15:11 -0500 Message-Id: <20221107071511.2764628-8-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove unused compatibles from i.MXRT1050.dtsi. Change GPT clock-names to match documentation. Cc: Giulio Benetti Signed-off-by: Jesse Taube --- arch/arm/boot/dts/imxrt1050.dtsi | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050= .dtsi index 03e6a858a7be..8d79de239046 100644 --- a/arch/arm/boot/dts/imxrt1050.dtsi +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -29,7 +29,7 @@ osc3M: osc3M { =20 soc { lpuart1: serial@40184000 { - compatible =3D "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; + compatible =3D "fsl,imxrt1050-lpuart"; reg =3D <0x40184000 0x4000>; interrupts =3D <20>; clocks =3D <&clks IMXRT1050_CLK_LPUART1>; @@ -40,7 +40,6 @@ lpuart1: serial@40184000 { iomuxc: pinctrl@401f8000 { compatible =3D "fsl,imxrt1050-iomuxc"; reg =3D <0x401f8000 0x4000>; - fsl,mux_mask =3D <0x7>; }; =20 anatop: anatop@400d8000 { @@ -83,7 +82,7 @@ edma1: dma-controller@400e8000 { }; =20 usdhc1: mmc@402c0000 { - compatible =3D "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + compatible =3D "fsl,imxrt1050-usdhc"; reg =3D <0x402c0000 0x4000>; interrupts =3D <110>; clocks =3D <&clks IMXRT1050_CLK_IPG_PDOF>, @@ -150,11 +149,11 @@ gpio5: gpio@400c0000 { }; =20 gpt: timer@401ec000 { - compatible =3D "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + compatible =3D "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt"; reg =3D <0x401ec000 0x4000>; interrupts =3D <100>; - clocks =3D <&osc3M>; - clock-names =3D "per"; + clocks =3D <&osc3M>, <&osc3M>; + clock-names =3D "ipg", "per"; }; }; }; --=20 2.37.2