From nobody Thu Nov 14 07:42:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F664C433FE for ; Sun, 6 Nov 2022 08:51:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229873AbiKFIvD (ORCPT ); Sun, 6 Nov 2022 03:51:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229797AbiKFIus (ORCPT ); Sun, 6 Nov 2022 03:50:48 -0500 Received: from mxout1.routing.net (mxout1.routing.net [IPv6:2a03:2900:1:a::a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 095C5E0D1; Sun, 6 Nov 2022 01:50:46 -0700 (PDT) Received: from mxbox3.masterlogin.de (unknown [192.168.10.78]) by mxout1.routing.net (Postfix) with ESMTP id BEC0B40408; Sun, 6 Nov 2022 08:50:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1667724644; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rJ3IqB4e94p/UqzhZv1jkPQ38OMRpHHjnAFsokFJqKg=; b=vmvRsF0H++ooVCuI4QhQIl0w3C5i1LsWVxzYPgP4Nn6T3ZW7Gz3KMFp+KOwd/RXbBMbd2W r6U/B5CPpzfhcLW7ff62Zi/8jm8+wIzdpwBmQD9QgFdO+SOzjJ/yi6tkGaWmu2DBKVDOzS Qxbfg0zR/QpcWww8m9ScUBs3VHqHLWU= Received: from frank-G5.. (fttx-pool-80.245.79.199.bambit.de [80.245.79.199]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 1921A3608D6; Sun, 6 Nov 2022 08:50:44 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Matthias Brugger , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sam Shih , Jieyy Yang Subject: [RFC v3 07/11] arm64: dts: mt7986: add pcie related device nodes Date: Sun, 6 Nov 2022 09:50:30 +0100 Message-Id: <20221106085034.12582-8-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106085034.12582-1-linux@fw-web.de> References: <20221106085034.12582-1-linux@fw-web.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: 3c55aecf-50e0-46c2-a0eb-79f1fdfe2ed3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sam Shih This patch adds PCIe support for MT7986. Signed-off-by: Jieyy Yang Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich --- changes compared to sams original version: - add clock-names to pcie node - update clocks to new binding --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot= /dts/mediatek/mt7986a-rfb.dts index e1a0331aaa5f..01fa08c57c39 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -102,6 +102,15 @@ &mmc0 { non-removable; no-sd; no-sdio; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins>; + status =3D "okay"; +}; + +&pcie_phy { status =3D "okay"; }; =20 @@ -164,6 +173,13 @@ conf-rst { }; }; =20 + pcie_pins: pcie-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + spi_flash_pins: spi-flash-pins { mux { function =3D "spi"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7986a.dtsi index a1a788db113a..eb9023857a05 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&gic>; @@ -313,6 +314,57 @@ mmc0: mmc@11230000 { status =3D "disabled"; }; =20 + pcie: pcie@11280000 { + compatible =3D "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x00 0x11280000 0x00 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x10000000>; + clocks =3D <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names =3D "pl_250m", "tl_26m", "peri_26m", "top_133m"; + status =3D "disabled"; + + phys =3D <&pcie_port PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + pcie_phy: t-phy@11c00000 { + compatible =3D "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + pcie_port: pcie-phy@11c00000 { + reg =3D <0 0x11c00000 0 0x20000>; + clocks =3D <&clk40m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + usb_phy: t-phy@11e10000 { compatible =3D "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; --=20 2.34.1