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(fttx-pool-80.245.79.199.bambit.de [80.245.79.199]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 6642C360707; Sun, 6 Nov 2022 08:50:45 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Matthias Brugger , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC v3 09/11] arm64: dts: mt7986: add Bananapi R3 Date: Sun, 6 Nov 2022 09:50:32 +0100 Message-Id: <20221106085034.12582-10-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106085034.12582-1-linux@fw-web.de> References: <20221106085034.12582-1-linux@fw-web.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: f8b65ebf-df8e-4a7b-a06e-ffa77a1ae7ea Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add support for Bananapi R3 SBC. - SD/eMMC support (switching first 4 bits of data-bus with sw6/D) - all rj45 ports and both SFP working (eth1/lan4) - all USB-Ports + SIM-Slot tested - i2c and all uarts tested - wifi tested (with eeprom calibration data) Signed-off-by: Frank Wunderlich --- SPI-NAND/NOR switched (CS by sw5/C) not yet included this is done with DT-Overlays in my tree, don't know how to do it in upstream the right way...added dts files for dtbo and added them with dtbo extension to Makefile works. changes: v3: - rename factory-key to reset-key - add dcin regulator and add it as input for 3v3 (with renaming) - remove memory-node - dropped wifi eeprom (calibration) data - move mmc0 pinctrl to common dtsi and drop sdcard comment - change mmc pull-up/down to have generic bias-pull* v2: - remove pcie to be added later (discussion about clocks) - some fixes based on suggestions on ML - add key suffix like it's done in mt7622-bpi-r64 devicetree - add dash in sfp node names - use reg as unit for switch-node - drop "-3-4" suffix from i2c-pins node name - fix order in Makefile --- arch/arm64/boot/dts/mediatek/Makefile | 2 + .../mediatek/mt7986a-bananapi-bpi-r3-emmc.dts | 31 ++ .../mediatek/mt7986a-bananapi-bpi-r3-sd.dts | 25 + .../dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi | 441 ++++++++++++++++++ 4 files changed, 499 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-em= mc.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd= .dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dt= si diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 0ec90cb3ef28..e8902f2cc58f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -7,6 +7,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-bananapi-bpi-r3-emmc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-bananapi-bpi-r3-sd.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8167-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts = b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts new file mode 100644 index 000000000000..a0ca35b5977e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include +#include + +#include "mt7986a-bananapi-bpi-r3.dtsi" + +/ { + model =3D "Bananapi BPI-R3 (emmc)"; +}; + +&mmc0 { + bus-width =3D <8>; + max-frequency =3D <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay =3D <0x14014>; + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status =3D "okay"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts b/= arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts new file mode 100644 index 000000000000..06e4691cb815 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include +#include + +#include "mt7986a-bananapi-bpi-r3.dtsi" + +/ { + model =3D "Bananapi BPI-R3 (sdmmc)"; +}; + +&mmc0 { + bus-width =3D <4>; + max-frequency =3D <52000000>; + cap-sd-highspeed; + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <®_1p8v>; + status =3D "okay"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi b/ar= ch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi new file mode 100644 index 000000000000..93ac67641351 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi @@ -0,0 +1,441 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Authors: Sam.Shih + * Frank Wunderlich + * Daniel Golle + */ + +/dts-v1/; +#include +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model =3D "Bananapi BPI-R3"; + compatible =3D "bananapi,bpi-r3", "mediatek,mt7986a"; + + aliases { + serial0 =3D &uart0; + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + dcin: regulator-12vd { + compatible =3D "regulator-fixed"; + regulator-name =3D "12vd"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + reset-key { + label =3D "reset"; + linux,code =3D ; + gpios =3D <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps-key { + label =3D "wps"; + linux,code =3D ; + gpios =3D <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + /* i2c of the left SFP cage (wan) */ + i2c_sfp1: i2c-gpio-0 { + compatible =3D "i2c-gpio"; + sda-gpios =3D <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + /* i2c of the right SFP cage (lan) */ + i2c_sfp2: i2c-gpio-1 { + compatible =3D "i2c-gpio"; + sda-gpios =3D <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + + green_led: led-0 { + color =3D ; + function =3D LED_FUNCTION_POWER; + gpios =3D <&pio 69 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + + blue_led: led-1 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pio 86 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1.8vd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <&dcin>; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "3.3vd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <&dcin>; + }; + + reg_5v: regulator-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-5p1"; + regulator-min-microvolt =3D <5100000>; + regulator-max-microvolt =3D <5100000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <&dcin>; + }; + + /* left SFP cage (wan) */ + sfp1: sfp-1 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp1>; + los-gpio =3D <&pio 46 GPIO_ACTIVE_HIGH>; + moddef0-gpio =3D <&pio 49 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&pio 20 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + /* right SFP cage (lan) */ + sfp2: sfp-2 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp2>; + los-gpios =3D <&pio 31 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&pio 47 GPIO_ACTIVE_LOW>; + tx-disable-gpios =3D <&pio 15 GPIO_ACTIVE_HIGH>; + tx-fault-gpios =3D <&pio 48 GPIO_ACTIVE_HIGH>; + }; +}; + +&crypto { + status =3D "okay"; +}; + +ð { + status =3D "okay"; + + gmac0: mac@0 { + compatible =3D "mediatek,eth-mac"; + reg =3D <0>; + phy-mode =3D "2500base-x"; + + fixed-link { + speed =3D <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible =3D "mediatek,eth-mac"; + reg =3D <1>; + phy-mode =3D "2500base-x"; + sfp =3D <&sfp1>; + managed =3D "in-band-status"; + }; + + mdio: mdio-bus { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; +}; + +&mdio { + switch: switch@31 { + compatible =3D "mediatek,mt7531"; + reg =3D <31>; + reset-gpios =3D <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&mmc0 { + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_pins_default>; + pinctrl-1 =3D <&mmc0_pins_uhs>; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c_pins>; + status =3D "okay"; +}; + +&pio { + i2c_pins: i2c-pins { + mux { + function =3D "i2c"; + groups =3D "i2c"; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function =3D "emmc"; + groups =3D "emmc_51"; + }; + conf-cmd-dat { + pins =3D "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength =3D <4>; + bias-pull-up =3D ; /* pull-up 10K */ + }; + conf-clk { + pins =3D "EMMC_CK"; + drive-strength =3D <6>; + bias-pull-down =3D ; /* pull-down 50K */ + }; + conf-ds { + pins =3D "EMMC_DSL"; + bias-pull-down =3D ; /* pull-down 50K */ + }; + conf-rst { + pins =3D "EMMC_RSTB"; + drive-strength =3D <4>; + bias-pull-up =3D ; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function =3D "emmc"; + groups =3D "emmc_51"; + }; + conf-cmd-dat { + pins =3D "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength =3D <4>; + bias-pull-up =3D ; /* pull-up 10K */ + }; + conf-clk { + pins =3D "EMMC_CK"; + drive-strength =3D <6>; + bias-pull-down =3D ; /* pull-down 50K */ + }; + conf-ds { + pins =3D "EMMC_DSL"; + bias-pull-down =3D ; /* pull-down 50K */ + }; + conf-rst { + pins =3D "EMMC_RSTB"; + drive-strength =3D <4>; + bias-pull-up =3D ; /* pull-up 10K */ + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function =3D "spi"; + groups =3D "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function =3D "spi"; + groups =3D "spi1_0"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function =3D "uart"; + groups =3D "uart1_rx_tx"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function =3D "uart"; + groups =3D "uart2_0_rx_tx"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function =3D "wifi"; + groups =3D "wf_2g", "wf_5g"; + }; + conf { + pins =3D "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength =3D <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function =3D "wifi"; + groups =3D "wf_dbdc"; + }; + conf { + pins =3D "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength =3D <4>; + }; + }; + + wf_led_pins: wf-led-pins { + mux { + function =3D "led"; + groups =3D "wifi_led"; + }; + }; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi_flash_pins>; + cs-gpios =3D <0>, <0>; + status =3D "okay"; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spic_pins>; + cs-gpios =3D <0>, <0>; + status =3D "okay"; +}; + +&ssusb { + vusb33-supply =3D <®_3p3v>; + vbus-supply =3D <®_5v>; + status =3D "okay"; +}; + +&switch { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "wan"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan0"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan1"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan2"; + }; + + port@4 { + reg =3D <4>; + label =3D "lan3"; + }; + + port5: port@5 { + reg =3D <5>; + label =3D "lan4"; + phy-mode =3D "2500base-x"; + sfp =3D <&sfp2>; + managed =3D "in-band-status"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "2500base-x"; + + fixed-link { + speed =3D <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&trng { + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; + status =3D "okay"; +}; + +&usb_phy { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; + +&wifi { + status =3D "okay"; + pinctrl-names =3D "default", "dbdc"; + pinctrl-0 =3D <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 =3D <&wf_dbdc_pins>, <&wf_led_pins>; +}; + --=20 2.34.1