From nobody Sat Sep 21 09:39:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD00BC433FE for ; Sat, 5 Nov 2022 09:04:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229640AbiKEJEK (ORCPT ); Sat, 5 Nov 2022 05:04:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229477AbiKEJEH (ORCPT ); Sat, 5 Nov 2022 05:04:07 -0400 Received: from mxout3.routing.net (mxout3.routing.net [IPv6:2a03:2900:1:a::8]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE4AD1F9C7; Sat, 5 Nov 2022 02:04:05 -0700 (PDT) Received: from mxbox2.masterlogin.de (unknown [192.168.10.89]) by mxout3.routing.net (Postfix) with ESMTP id 6AE6F604CC; Sat, 5 Nov 2022 09:04:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1667639044; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=tro3szDJlWgVsZyFublVkVtfBEGp54Hr61ecPAwf2UU=; b=AwGhp1o7D+xhVDW7hM8g6httpx//aJuAElPaQH7UHP3BwqrlKXGC2uPVG0QakX34kQrZ1g 4NFdx7SlTMVCXfnFffFD5wMhOB1RvMY/aVAmyvQkbT24Clv/wCnJgOx+BC6OnFbO68tJcp twtK6VXg5Tj7ppvMtAj1E0SkuKv7yoU= Received: from frank-G5.. (fttx-pool-217.61.159.50.bambit.de [217.61.159.50]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id 7DCC6100786; Sat, 5 Nov 2022 09:04:03 +0000 (UTC) From: Frank Wunderlich To: "linux-mediatek @ lists . infradead . org Linus Walleij" , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Sam Shih , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Frank Wunderlich Subject: [PATCH v3] dt-bindings: pinctrl: update uart/mmc bindings for MT7986 SoC Date: Sat, 5 Nov 2022 10:03:58 +0100 Message-Id: <20221105090359.11249-1-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: c763ee95-2626-41c2-8a50-bcf2deb0d352 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Some pinmux pins of the mt7986 pinctrl driver is composed of multiple pinctrl groups, the original binding only allows one pinctrl group per dts node, this patch sets "maxItems" for these groups and add new examples to the binding documentation. Fixes: 65916a1ca90a ("dt-bindings: pinctrl: update bindings for MT7986 SoC") Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich --- v3: - squashed version from sam - v2 was ack'd by Krzysztof, but sams patch included updated emmc-names and different structure for uart to allow 2 pingroups v2: - wrap on col 80 --- .../pinctrl/mediatek,mt7986-pinctrl.yaml | 46 +++++++++++++++++-- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctr= l.yaml index 75766956cfad..b2b9c01efd70 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -87,6 +87,8 @@ patternProperties: "wifi_led" "led" 1, 2 "i2c" "i2c" 3, 4 "uart1_0" "uart" 7, 8, 9, 10 + "uart1_rx_tx" "uart" 42, 43 + "uart1_cts_rts" "uart" 44, 45 "pcie_clk" "pcie" 9 "pcie_wake" "pcie" 10 "spi1_0" "spi" 11, 12, 13, 14 @@ -98,9 +100,11 @@ patternProperties: "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 "spi1_1" "spi" 23, 24, 25, 26 - "uart1_2" "uart" 29, 30, 31, 32 + "uart1_2_rx_tx" "uart" 29, 30 + "uart1_2_cts_rts" "uart" 31, 32 "uart1_1" "uart" 23, 24, 25, 26 - "uart2_0" "uart" 29, 30, 31, 32 + "uart2_0_rx_tx" "uart" 29, 30 + "uart2_0_cts_rts" "uart" 31, 32 "spi0" "spi" 33, 34, 35, 36 "spi0_wp_hold" "spi" 37, 38 "uart1_3_rx_tx" "uart" 35, 36 @@ -157,7 +161,7 @@ patternProperties: then: properties: groups: - enum: [emmc, emmc_rst] + enum: [emmc_45, emmc_51] - if: properties: function: @@ -227,8 +231,12 @@ patternProperties: then: properties: groups: - enum: [uart1_0, uart1_1, uart1_2, uart1_3_rx_tx, - uart1_3_cts_rts, uart2_0, uart2_1, uart0, uart1, = uart2] + items: + enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1, + uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx, + uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts, + uart2_1, uart0, uart1, uart2] + maxItems: 2 - if: properties: function: @@ -362,6 +370,27 @@ examples: interrupt-parent =3D <&gic>; #interrupt-cells =3D <2>; =20 + pcie_pins: pcie-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function =3D "pwm"; + groups =3D "pwm0", "pwm1_0"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function =3D "spi"; + groups =3D "spi0", "spi0_wp_hold"; + }; + }; + uart1_pins: uart1-pins { mux { function =3D "uart"; @@ -369,6 +398,13 @@ examples: }; }; =20 + uart1_3_pins: uart1-3-pins { + mux { + function =3D "uart"; + groups =3D "uart1_3_rx_tx", "uart1_3_cts_rts"; + }; + }; + uart2_pins: uart2-pins { mux { function =3D "uart"; --=20 2.34.1