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([2601:586:5000:570:aad6:acd8:4ed9:299b]) by smtp.gmail.com with ESMTPSA id j8-20020a05620a288800b006fa4cac54a4sm3389016qkp.133.2022.11.04.11.21.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 11:21:13 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2] dt-bindings: clock: qcom,sdm845-lpasscc: convert to dtschema Date: Fri, 4 Nov 2022 14:21:08 -0400 Message-Id: <20221104182108.126515-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert Qualcomm SDM845 LPASS clock controller bindings to DT schema. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd --- Changes since v1: 1. Correct Bjorn's email. --- .../bindings/clock/qcom,lpasscc.txt | 26 ---------- .../bindings/clock/qcom,sdm845-lpasscc.yaml | 47 +++++++++++++++++++ 2 files changed, 47 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,sdm845-lpa= sscc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt b/Doc= umentation/devicetree/bindings/clock/qcom,lpasscc.txt deleted file mode 100644 index b9e9787045b9..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt +++ /dev/null @@ -1,26 +0,0 @@ -Qualcomm LPASS Clock Controller Binding ------------------------------------------------ - -Required properties : -- compatible : shall contain "qcom,sdm845-lpasscc" -- #clock-cells : from common clock binding, shall contain 1. -- reg : shall contain base register address and size, - in the order - Index-0 maps to LPASS_CC register region - Index-1 maps to LPASS_QDSP6SS register region - -Optional properties : -- reg-names : register names of LPASS domain - "cc", "qdsp6ss". - -Example: - -The below node has to be defined in the cases where the LPASS peripheral l= oader -would bring the subsystem out of reset. - - lpasscc: clock-controller@17014000 { - compatible =3D "qcom,sdm845-lpasscc"; - reg =3D <0x17014000 0x1f004>, <0x17300000 0x200>; - reg-names =3D "cc", "qdsp6ss"; - #clock-cells =3D <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-lpasscc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sdm845-lpasscc.yaml new file mode 100644 index 000000000000..a96fd837c70a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-lpasscc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdm845-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM845 LPASS Clock Controller + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm SDM845 LPASS (Low Power Audio SubSystem) Clock Controller. + + See also:: include/dt-bindings/clock/qcom,lpass-sdm845.h + +properties: + compatible: + const: qcom,sdm845-lpasscc + + '#clock-cells': + const: 1 + + reg: + maxItems: 2 + + reg-names: + items: + - const: cc + - const: qdsp6ss + +required: + - compatible + - '#clock-cells' + - reg + - reg-names + +additionalProperties: false + +examples: + - | + clock-controller@17014000 { + compatible =3D "qcom,sdm845-lpasscc"; + reg =3D <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names =3D "cc", "qdsp6ss"; + #clock-cells =3D <1>; + }; --=20 2.34.1