From nobody Thu Apr 9 12:33:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD27FC4332F for ; Fri, 4 Nov 2022 17:22:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231358AbiKDRWs (ORCPT ); Fri, 4 Nov 2022 13:22:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231814AbiKDRWT (ORCPT ); Fri, 4 Nov 2022 13:22:19 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3ABA419A0; Fri, 4 Nov 2022 10:22:09 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 47DC566029BF; Fri, 4 Nov 2022 17:22:06 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582527; bh=9L1mfVQGnIjU2vBQIpRBmFl5JvPjKQm/Tn0A9zXl7Ug=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q5vImTDCznUDBRBoTXwbj0exgf33oRitmreiMjgymRP/DAgFsMDcMckrbjWIvZlwT lCDFkGAc9cBu4Oxk2nUCNbRz1vUEpe9ZQ9nQ4Z9HBC7LO1cLqLpvZeEG3t5GvGh9io 42OSdkfDCyHpQlVSgqVazSD61N1GfSv+sGfnNyA7UDLAhN0dJNsidxtsGXi9KiC/az y2yc3udyktdV9L0QA3qKeTq20SQYBVlUy97XuU9z61vRttr4wW5D1q5kI/r5TiOxql 9V/8V2EPnxazvM/xZHb/J2O330sysskw/d/SiJVz3XVq24AMbvZBdWspUkX20wv/tJ 0DJUVi1RJx9Cw== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno , AngeloGioacchino Del Regno Subject: [PATCH 8/9] arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs Date: Fri, 4 Nov 2022 18:21:21 +0100 Message-Id: <20221104172122.252761-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: AngeloGioacchino Del Regno This commit adds device trees for MSM8956 and MSM8976 SoCs. They are *almost* identical, with minor differences, such as MSM8956 having two A72 cores less. However, there is a bug in Sony Loire bootloader that requires presence of all 8 cores in the cpu{} node, so these will not be deleted. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Co-developed-by: Marijn Suijten Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8956.dtsi | 18 + arch/arm64/boot/dts/qcom/msm8976.dtsi | 1208 +++++++++++++++++++++++++ 2 files changed, 1226 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8956.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8976.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qc= om/msm8956.dtsi new file mode 100644 index 000000000000..eb2c1345172c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +#include "msm8976.dtsi" + +&pmu { + interrupts =3D ; +}; + +/* + * You might be wondering.. why is it so empty out there? + * Well, the SoCs are almost identical. + */ diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qc= om/msm8976.dtsi new file mode 100644 index 000000000000..e084a3a78f18 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -0,0 +1,1208 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + enable-method =3D "psci"; + cpu-idle-states =3D <&little_cpu_sleep_0>; + capacity-dmips-mhz =3D <573>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + CPU1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + enable-method =3D "psci"; + cpu-idle-states =3D <&little_cpu_sleep_0>; + capacity-dmips-mhz =3D <573>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + CPU2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + enable-method =3D "psci"; + cpu-idle-states =3D <&little_cpu_sleep_0>; + capacity-dmips-mhz =3D <573>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + CPU3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + enable-method =3D "psci"; + cpu-idle-states =3D <&little_cpu_sleep_0>; + capacity-dmips-mhz =3D <573>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + CPU4: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x100>; + enable-method =3D "psci"; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + CPU5: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x101>; + enable-method =3D "psci"; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + CPU6: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x102>; + enable-method =3D "psci"; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + CPU7: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x103>; + enable-method =3D "psci"; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&CPU4>; + }; + + core1 { + cpu =3D <&CPU5>; + }; + + core2 { + cpu =3D <&CPU6>; + }; + + core3 { + cpu =3D <&CPU7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "little-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <181>; + exit-latency-us =3D <149>; + min-residency-us =3D <703>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-retention"; + arm,psci-suspend-param =3D <0x00000002>; + entry-latency-us =3D <142>; + exit-latency-us =3D <99>; + min-residency-us =3D <242>; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <158>; + exit-latency-us =3D <144>; + min-residency-us =3D <863>; + local-timer-stop; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8976", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", "bus", "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu: pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + cont_splash_mem: memory@83000000 { + reg =3D <0x0 0x83000000 0x0 0x2800000>; + }; + + ext_region: memory@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x500000>; + no-map; + }; + + smem: memory@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + removed_mem: memory@86400000 { + reg =3D <0x0 0x86400000 0x0 0x800000>; + no-map; + }; + + mpss_region: memory@86c00000 { + reg =3D <0x0 0x86c00000 0x0 0x5600000>; + no-map; + }; + + lpass_region: memory@8c200000 { + reg =3D <0x0 0x8c200000 0x0 0x1800000>; + no-map; + }; + + venus_region: memory@8da00000 { + reg =3D <0x0 0x8da00000 0x0 0x2600000>; + no-map; + }; + + tz_apps: memory@8dd00000 { + reg =3D <0x0 0x8dd00000 0x0 0x1400000>; + no-map; + }; + }; + + smp2p-hexagon { + compatible =3D "qcom,smp2p"; + interrupts =3D ; + qcom,ipc =3D <&apcs 8 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + qcom,smem =3D <443>, <429>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + interrupts =3D ; + qcom,ipc =3D <&apcs 8 13>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + qcom,smem =3D <435>, <428>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + interrupts =3D ; + qcom,ipc =3D <&apcs 8 17>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + qcom,smem =3D <451>, <431>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smd { + compatible =3D "qcom,smd"; + + rpm { + interrupts =3D ; + qcom,ipc =3D <&apcs 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8976"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8976", "qcom,rpmcc"; + #clock-cells =3D <1>; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8976-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level =3D ; + }; + + rpmpd_opp_turbo_high: opp111 { + opp-level =3D ; + }; + }; + }; + }; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + qcom,ipc-1 =3D <&apcs 8 12>; + qcom,ipc-2 =3D <&apcs 8 9>; + qcom,ipc-3 =3D <&apcs 8 18>; + + apps_smsm: apps@0 { + reg =3D <0>; + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D <0 290 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0xffffffff>; + compatible =3D "simple-bus"; + + rng@22000 { + compatible =3D "qcom,prng"; + reg =3D <0x00022000 0x140>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x00060000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x0006c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", "ahb", "sleep"; + resets =3D <&gcc RST_QUSB2_PHY_BCR>, + <&gcc RST_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", "por"; + status =3D "disabled"; + }; + + qfprom: qfprom@a4000 { + compatible =3D "qcom,msm8976-qfprom", "qcom,qfprom"; + reg =3D <0x000a4000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_caldata: caldata@218 { + reg =3D <0x218 0x18>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8976-tsens", "qcom,tsens-v1"; + reg =3D <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + interrupts =3D ; + interrupt-names =3D "uplow"; + nvmem-cells =3D <&tsens_caldata>; + nvmem-cell-names =3D "calib"; + #qcom,sensors =3D <11>; + #thermal-sensor-cells =3D <1>; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8976-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + spi1_default: spi0-default-state { + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "blsp_spi1"; + drive-strength =3D <12>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio2"; + function =3D "blsp_spi1"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + spi1_sleep: spi0-sleep-state { + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cs-pins { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_uart2_active: blsp2-uart2-active-state { + pins =3D "gpio20", "gpio21"; + function =3D "blsp_uart6"; + drive-strength =3D <4>; + bias-disable; + }; + + blsp2_uart2_sleep: blsp2-uart2-sleep-state { + pins =3D "gpio20", "gpio21"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ + blsp2_i2c2_default: blsp2-i2c2-default-state { + pins =3D "gpio22", "gpio23"; + function =3D "blsp_i2c6"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { + pins =3D "gpio22", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c4_default: blsp2-i2c4-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c8"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8976"; + reg =3D <0x01800000 0x80000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + + assigned-clocks =3D <&gcc GPLL3>; + assigned-clock-rates =3D <1100000000>; + + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + clock-names =3D "xo", + "xo_a", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8976", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x1000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x2100>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts =3D ; + interrupt-names =3D "periph_irq"; + qcom,channel =3D <0>; + qcom,ee =3D <0>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + cell-index =3D <0>; + }; + + sdhc_1: mmc@7824000 { + compatible =3D "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x500>, <0x07824000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + + bus-width =3D <8>; + non-removable; + status =3D "disabled"; + }; + + sdhc_2: mmc@7864000 { + compatible =3D "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + + bus-width =3D <4>; + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + }; + + blsp1_uart1: serial@78af000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078af000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + blsp1_spi1: spi@78b5000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b5000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi1_default>; + pinctrl-1 =3D <&spi1_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_i2c2_default>; + pinctrl-1 =3D <&blsp1_i2c2_default>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b8000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_i2c4_default>; + pinctrl-1 =3D <&blsp1_i2c4_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + otg: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts =3D , + ; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc RST_USB_HS_BCR>; + reset-names =3D "core"; + ahb-burst-config =3D <0>; + dr_mode =3D "peripheral"; + phy_type =3D "ulpi"; + phy-names =3D "usb-phy"; + phys =3D <&usb_hs_phy>; + status =3D "disabled"; + #reset-cells =3D <1>; + }; + + sdhc_3: mmc@7a24000 { + compatible =3D "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07a24900 0x11c>, <0x07a24000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "core", "xo"; + bus-width =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07ac4000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + }; + + blsp2_uart2: serial@7af0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x07af0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + blsp2_i2c2: i2c@7af6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp2_i2c2_default>; + pinctrl-1 =3D <&blsp2_i2c2_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp2_i2c4: i2c@7af8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af8000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + clock-frequency =3D <400000>; + dmas =3D <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp2_i2c4_default>; + pinctrl-1 =3D <&blsp2_i2c4_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x0b000000 0x1000>, <0x0b002000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + apcs: syscon@b011000 { + compatible =3D "syscon"; + reg =3D <0x0b011000 0x1000>; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clock-frequency =3D <19200000>; + + frame@b121000 { + reg =3D <0x0b121000 0x1000>, <0x0b122000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@b123000 { + reg =3D <0x0b123000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + status =3D "disabled"; + }; + + frame@b124000 { + reg =3D <0x0b124000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + status =3D "disabled"; + }; + + frame@b125000 { + reg =3D <0x0b125000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + status =3D "disabled"; + }; + + frame@b126000 { + reg =3D <0x0b126000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + status =3D "disabled"; + }; + + frame@b127000 { + reg =3D <0x0b127000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + status =3D "disabled"; + }; + + frame@b128000 { + reg =3D <0x0b128000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + status =3D "disabled"; + }; + }; + + imem: imem@8600000 { + compatible =3D "simple-mfd"; + reg =3D <0x08600000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0 0x08600000 0x1000>; + + pil-reloc@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 1>; + trips { + modem_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + qdsp-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 2>; + trips { + qdsp_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + cam-isp-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 3>; + trips { + cam_isp_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 4>; + + trips { + cpu4_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + cpu4_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu4_crit: cpu-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 5>; + + trips { + cpu5_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + cpu5_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu5_crit: cpu-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 6>; + + trips { + cpu6_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + cpu6_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu6_crit: cpu-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 7>; + + trips { + cpu7_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + cpu7_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu7_crit: cpu-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + big-l2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 8>; + + trips { + l2_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + l2_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + l2_crit: l2-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 9>; + + trips { + cpu0_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + cpu0_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu0_crit: cpu-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 10>; + + trips { + gpu_alert0: trip-point0 { + temperature =3D <50000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + gpu_alert1: trip-point1 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu_crit: gpu-crit { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; +}; --=20 2.37.2