From nobody Thu Apr 9 09:02:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA0EBC4332F for ; Thu, 3 Nov 2022 18:00:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232036AbiKCR76 (ORCPT ); Thu, 3 Nov 2022 13:59:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232042AbiKCR71 (ORCPT ); Thu, 3 Nov 2022 13:59:27 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53C972628 for ; Thu, 3 Nov 2022 10:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498359; x=1699034359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IRafYvcGTb3XRIZ8BF10OMlvhWCpsdfukSgZuf8/1v8=; b=bIWFEOAeCGrPWyjKFHyXRC4UxDwtcJ3DglJJHuWAwJfDXrfHh9E0/wzM trifDp6L+lVtU0fBUvQ5Q7Bm3oo8D9P1ku7GM/7Dof/TFIDbcEP5hbH2a bJx26hsohmpVTRpjjlsgmpOJuX3nS6ZgnQTD94ipwORzdSsjEyi7uOSK5 D4RGpriRcl2eKseFNp7gwzunTi9DEMmJbX5mcjBE0FH2eDDr3TcKFCarr Vu33aq6MzyuvE4diI2KHzIG84wOodvOrlVbp5Pt08yB7TLE6KxxwrsE4R lV2a0xwfrJE2c11Hmyn87LlaPGd6NmvLC4ewGKnUBYjJusjTp/HY3PLUw w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476963" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476963" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762540" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762540" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:17 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 01/13] x86/microcode/intel: Prevent printing updated microcode rev multiple times Date: Thu, 3 Nov 2022 17:58:49 +0000 Message-Id: <20221103175901.164783-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Commit b6f86689d5b7 ("x86/microcode: Rip out the subsys interface gunk") introduced a race where all CPUs follow this call chain: microcode_init()->schedule_on_each_cpu(setup_online_cpu)->collect_cpu_info This results in console spam where multiple CPUs print the signature. [ 33.688639] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 [ 33.688659] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 [ 33.688660] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 Fix by making sure only boot CPU prints the message. Fixes: b6f86689d5b7 ("x86/microcode: Rip out the subsys interface gunk") Reported-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 8c35c70029bf..8f7f8dd6680e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -680,6 +680,7 @@ void reload_ucode_intel(void) =20 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { + bool bsp =3D cpu_num =3D=3D boot_cpu_data.cpu_index; static struct cpu_signature prev; struct cpuinfo_x86 *c =3D &cpu_data(cpu_num); unsigned int val[2]; @@ -696,8 +697,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_sig= nature *csig) =20 csig->rev =3D c->microcode; =20 - /* No extra locking on prev, races are harmless. */ - if (csig->sig !=3D prev.sig || csig->pf !=3D prev.pf || csig->rev !=3D pr= ev.rev) { + if (bsp && csig->rev !=3D prev.rev) { pr_info("sig=3D0x%x, pf=3D0x%x, revision=3D0x%x\n", csig->sig, csig->pf, csig->rev); prev =3D *csig; --=20 2.34.1