From nobody Sat Sep 21 12:35:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77A0CC433FE for ; Thu, 3 Nov 2022 02:57:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231408AbiKCC5Y (ORCPT ); Wed, 2 Nov 2022 22:57:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231244AbiKCC5M (ORCPT ); Wed, 2 Nov 2022 22:57:12 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58AA8B494; Wed, 2 Nov 2022 19:57:11 -0700 (PDT) X-UUID: 04637ab86aee4656b8bf92dffdb795ab-20221103 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=4dZ2hELix6uqbfomrJGOrcGfF37xwYRVvGq3rzYT48w=; b=FMgKIxljPzCkcaoYH6TsK4Fwr3DNttdU76dv/ukJfGITvD2m08jCSLzMVdpmP39r+ubaN5PTSCWmBztxemB+go6F/ZsHqRhulWEvAPnSeHahC/cZ0Z/wKWhtZ1fDdASF0MreqiHWBj5c5fHcyM/vivOml9SsAk9ETtiBi6Qjk+0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:003d1042-3376-4249-bbd0-351bea4e718e,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:62cd327,CLOUDID:e2ee7581-3116-4fbc-b86b-83475c3df513,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 04637ab86aee4656b8bf92dffdb795ab-20221103 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1688554991; Thu, 03 Nov 2022 10:57:06 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 3 Nov 2022 10:57:04 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 3 Nov 2022 10:57:04 +0800 From: Tinghan Shen To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Tinghan Shen , Irui Wang Subject: [PATCH v5 3/3] arm64: dts: mt8195: Add venc node Date: Thu, 3 Nov 2022 10:56:56 +0800 Message-ID: <20221103025656.8714-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221103025656.8714-1-tinghan.shen@mediatek.com> References: <20221103025656.8714-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add venc node for mt8195 SoC. Signed-off-by: Irui Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 7d74a5211091..dbfc15174de3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2109,6 +2109,30 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC>; }; =20 + venc: video-codec@1a020000 { + compatible =3D "mediatek,mt8195-vcodec-enc"; + reg =3D <0 0x1a020000 0 0x10000>; + iommus =3D <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts =3D ; + mediatek,scp =3D <&scp>; + clocks =3D <&vencsys CLK_VENC_VENC>; + clock-names =3D "venc_sel"; + assigned-clocks =3D <&topckgen CLK_TOP_VENC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible =3D "mediatek,mt8195-vencsys_core1"; reg =3D <0 0x1b000000 0 0x1000>; --=20 2.18.0