From nobody Fri Dec 19 16:59:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15ACBC4332F for ; Thu, 3 Nov 2022 02:51:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231305AbiKCCvA (ORCPT ); Wed, 2 Nov 2022 22:51:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230312AbiKCCuq (ORCPT ); Wed, 2 Nov 2022 22:50:46 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F70E11158; Wed, 2 Nov 2022 19:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667443845; x=1698979845; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mU95m5Erwp5k3SxNIlFspBtJjiX62AILgoyTbwZv4TE=; b=MH0yXVKhnJDtaSjphCnhzHs1x6vLmkCCix/JKaj6pNLyWjw+aM1wvQMC 82ZQH1yOrB2cUcH1zt6RDrqSED/whJrCblq53wCefBBbjbj/OtB1uu8ts xCrP5j8ZOQPXhc1Ttxdp6y+sMKg3QYQHZthUK/TTTMiu/OHpzjhlKp7td keCG/E59Sg2uakO1pffa+IidcXYGRuhiyaEqsUKjMfQOd3fT6gxJG6ref MtW49+Ou3vqbZO5fHtAhWAl2cdnvhJdjwkCCQ3PAO8KhFUV7J5HgH5HH+ n9R5/zjJOD7U0g3c7IS0iba/s+aXgZJ5hLjckA3DCLTQ0YTFYCaM82xow A==; X-IronPort-AV: E=McAfee;i="6500,9779,10519"; a="308289825" X-IronPort-AV: E=Sophos;i="5.95,235,1661842800"; d="scan'208";a="308289825" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 19:50:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10519"; a="698047877" X-IronPort-AV: E=Sophos;i="5.95,235,1661842800"; d="scan'208";a="698047877" Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by fmsmga008.fm.intel.com with ESMTP; 02 Nov 2022 19:50:40 -0700 From: Jiaxi Chen To: kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com, ndesaulniers@google.com, alexandre.belloni@bootlin.com, peterz@infradead.org, jpoimboe@kernel.org, chang.seok.bae@intel.com, pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com, jmattson@google.com, sandipan.das@amd.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, fenghua.yu@intel.com, keescook@chromium.org, nathan@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] x86/cpufeatures: Replace [CPUID_DUMMY] in cpuid_leafs[] with the last leaf Date: Thu, 3 Nov 2022 10:50:24 +0800 Message-Id: <20221103025030.78371-3-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221103025030.78371-1-jiaxi.chen@linux.intel.com> References: <20221103025030.78371-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We now have empty feature bits in cpuid_leafs[12] CPUID_DUMMY, move the last one cpuid_leafs[19] CPUID_8000_001F_EAX to the hole and we can shorten the length of cpuid_leafs[] from current 20 to 19. Signed-off-by: Jiaxi Chen --- arch/x86/include/asm/cpufeature.h | 9 +++------ arch/x86/include/asm/cpufeatures.h | 18 +++++++++--------- arch/x86/include/asm/disabled-features.h | 3 +-- arch/x86/include/asm/required-features.h | 3 +-- 4 files changed, 14 insertions(+), 19 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index fbb4e7bd2288..bf273d796331 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -24,14 +24,13 @@ enum cpuid_leafs CPUID_7_0_EBX, CPUID_D_1_EAX, CPUID_LNX_4, - CPUID_DUMMY, + CPUID_8000_001F_EAX, CPUID_8000_0008_EBX, CPUID_6_EAX, CPUID_8000_000A_EDX, CPUID_7_ECX, CPUID_8000_0007_EBX, CPUID_7_EDX, - CPUID_8000_001F_EAX, }; =20 #define X86_CAP_FMT_NUM "%d:%d" @@ -93,9 +92,8 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \ REQUIRED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS !=3D 20)) + BUILD_BUG_ON_ZERO(NCAPINTS !=3D 19)) =20 #define DISABLED_MASK_BIT_SET(feature_bit) \ ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ @@ -117,9 +115,8 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \ DISABLED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS !=3D 20)) + BUILD_BUG_ON_ZERO(NCAPINTS !=3D 19)) =20 #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index cabe96df9555..df67a638f650 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -13,7 +13,7 @@ /* * Defines x86 CPU feature bits */ -#define NCAPINTS 20 /* N 32-bit words worth of info */ +#define NCAPINTS 19 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ =20 /* @@ -305,6 +305,14 @@ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ =20 +/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), w= ord 12 */ +#define X86_FEATURE_SME (12*32+ 0) /* AMD Secure Memory Encryption */ +#define X86_FEATURE_SEV (12*32+ 1) /* AMD Secure Encrypted Virtualizatio= n */ +#define X86_FEATURE_VM_PAGE_FLUSH (12*32+ 2) /* "" VM Page Flush MSR is su= pported */ +#define X86_FEATURE_SEV_ES (12*32+ 3) /* AMD Secure Encrypted Virtualizat= ion - Encrypted State */ +#define X86_FEATURE_V_TSC_AUX (12*32+ 9) /* "" Virtual TSC_AUX */ +#define X86_FEATURE_SME_COHERENT (12*32+10) /* "" AMD hardware-enforced ca= che coherency */ + /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ @@ -408,14 +416,6 @@ #define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILIT= IES MSR */ #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypa= ss Disable */ =20 -/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), w= ord 19 */ -#define X86_FEATURE_SME (19*32+ 0) /* AMD Secure Memory Encryption */ -#define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualizatio= n */ -#define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is su= pported */ -#define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualizat= ion - Encrypted State */ -#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ -#define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced ca= che coherency */ - /* * BUG word(s) */ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/as= m/disabled-features.h index 33d2cd04d254..192618cc0a42 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -110,7 +110,6 @@ DISABLE_ENQCMD) #define DISABLED_MASK17 0 #define DISABLED_MASK18 0 -#define DISABLED_MASK19 0 -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D 20) +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D 19) =20 #endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/as= m/required-features.h index aff774775c67..ff5e091efd2c 100644 --- a/arch/x86/include/asm/required-features.h +++ b/arch/x86/include/asm/required-features.h @@ -97,7 +97,6 @@ #define REQUIRED_MASK16 0 #define REQUIRED_MASK17 0 #define REQUIRED_MASK18 0 -#define REQUIRED_MASK19 0 -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D 20) +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D 19) =20 #endif /* _ASM_X86_REQUIRED_FEATURES_H */ --=20 2.27.0