From nobody Sat Sep 21 12:55:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DA17C433FE for ; Wed, 2 Nov 2022 19:06:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231803AbiKBTGa (ORCPT ); Wed, 2 Nov 2022 15:06:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231774AbiKBTGZ (ORCPT ); Wed, 2 Nov 2022 15:06:25 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC7262BF7; Wed, 2 Nov 2022 12:06:23 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7EA0E66028E3; Wed, 2 Nov 2022 19:06:21 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667415982; bh=1MQda8HO+asp2YDdSHvFW0nRegZrXBKBPzRi8BdE+0k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ULLNX7HM3PDSD3hhfnbIiHHV2zPfHshyTCPqPxXyOt6pqWgZ3PJ9rTVFFhFvpjIxw hitG0xcMiS+YZRXmZy0Qc8poyU9aeDKCewOGuauDkz5/i5r14QO20KsB0C1SxhT5dk iZE/Jz8RNlsmuRCBUeVopXIs+Fqwy3Dna2MU8owWFLgbDg1ZNHRCOIPSPHl9ap2wvV A7GdCLm7g1WdzBdpGuLBO6ZzZQOAIjnBJLpAAtT176GQCSJHgLuhVkwv7Vz7dszL2e ol2xj4deoIBTbuBTrnZVVU1GG4Y6IYxZvqw6WbUU97J9J76crg5O34qipE1qihMs9A kUxjF61ePCaiA== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 1/5] arm64: dts: mediatek: asurada: Add display regulators Date: Wed, 2 Nov 2022 15:06:07 -0400 Message-Id: <20221102190611.283546-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221102190611.283546-1-nfraprado@collabora.com> References: <20221102190611.283546-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the regulators present on the Asurada platform that are used to power the internal and external displays. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Signed-off-by: N=C3=ADcolas F. R. A. Prado --- (no changes since v2) Changes in v2: - Added missing vin-supply to regulators - Removed min/max-microvolt from regulators that are simple switches .../boot/dts/mediatek/mt8192-asurada.dtsi | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 4b314435f8fd..fafca7428539 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -23,6 +23,43 @@ memory@40000000 { reg =3D <0 0x40000000 0 0x80000000>; }; =20 + pp1000_dpbrdg: regulator-1v0-dpbrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1000_dpbrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1000_dpbrdg_en_pins>; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 19 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6359_vs2_buck_reg>; + }; + + pp1000_mipibrdg: regulator-1v0-mipibrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1000_mipibrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1000_mipibrdg_en_pins>; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 129 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6359_vs2_buck_reg>; + }; + + pp1800_dpbrdg: regulator-1v8-dpbrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_dpbrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1800_dpbrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 126 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6359_vio18_ldo_reg>; + }; + /* system wide LDO 1.8V power rail */ pp1800_ldo_g: regulator-1v8-g { compatible =3D "regulator-fixed"; @@ -34,6 +71,28 @@ pp1800_ldo_g: regulator-1v8-g { vin-supply =3D <&pp3300_g>; }; =20 + pp1800_mipibrdg: regulator-1v8-mipibrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_mipibrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1800_mipibrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 128 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6359_vio18_ldo_reg>; + }; + + pp3300_dpbrdg: regulator-3v3-dpbrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_dpbrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp3300_dpbrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 26 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp3300_g>; + }; + /* system wide switching 3.3V power rail */ pp3300_g: regulator-3v3-g { compatible =3D "regulator-fixed"; @@ -56,6 +115,17 @@ pp3300_ldo_z: regulator-3v3-z { vin-supply =3D <&ppvar_sys>; }; =20 + pp3300_mipibrdg: regulator-3v3-mipibrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_mipibrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp3300_mipibrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 127 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp3300_g>; + }; + /* separately switched 3.3V power rail */ pp3300_u: regulator-3v3-u { compatible =3D "regulator-fixed"; @@ -719,6 +789,48 @@ pins-wifi-kill { }; }; =20 + pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + pp3300_wlan_pins: pp3300-wlan-pins { pins-pcie-en-pp3300-wlan { pinmux =3D ; --=20 2.38.1