From nobody Sat Sep 21 09:30:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DA17C433FE for ; Wed, 2 Nov 2022 19:06:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231803AbiKBTGa (ORCPT ); Wed, 2 Nov 2022 15:06:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231774AbiKBTGZ (ORCPT ); Wed, 2 Nov 2022 15:06:25 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC7262BF7; Wed, 2 Nov 2022 12:06:23 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7EA0E66028E3; Wed, 2 Nov 2022 19:06:21 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667415982; bh=1MQda8HO+asp2YDdSHvFW0nRegZrXBKBPzRi8BdE+0k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ULLNX7HM3PDSD3hhfnbIiHHV2zPfHshyTCPqPxXyOt6pqWgZ3PJ9rTVFFhFvpjIxw hitG0xcMiS+YZRXmZy0Qc8poyU9aeDKCewOGuauDkz5/i5r14QO20KsB0C1SxhT5dk iZE/Jz8RNlsmuRCBUeVopXIs+Fqwy3Dna2MU8owWFLgbDg1ZNHRCOIPSPHl9ap2wvV A7GdCLm7g1WdzBdpGuLBO6ZzZQOAIjnBJLpAAtT176GQCSJHgLuhVkwv7Vz7dszL2e ol2xj4deoIBTbuBTrnZVVU1GG4Y6IYxZvqw6WbUU97J9J76crg5O34qipE1qihMs9A kUxjF61ePCaiA== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 1/5] arm64: dts: mediatek: asurada: Add display regulators Date: Wed, 2 Nov 2022 15:06:07 -0400 Message-Id: <20221102190611.283546-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221102190611.283546-1-nfraprado@collabora.com> References: <20221102190611.283546-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the regulators present on the Asurada platform that are used to power the internal and external displays. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Signed-off-by: N=C3=ADcolas F. R. A. Prado --- (no changes since v2) Changes in v2: - Added missing vin-supply to regulators - Removed min/max-microvolt from regulators that are simple switches .../boot/dts/mediatek/mt8192-asurada.dtsi | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 4b314435f8fd..fafca7428539 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -23,6 +23,43 @@ memory@40000000 { reg =3D <0 0x40000000 0 0x80000000>; }; =20 + pp1000_dpbrdg: regulator-1v0-dpbrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1000_dpbrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1000_dpbrdg_en_pins>; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 19 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6359_vs2_buck_reg>; + }; + + pp1000_mipibrdg: regulator-1v0-mipibrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1000_mipibrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1000_mipibrdg_en_pins>; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 129 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6359_vs2_buck_reg>; + }; + + pp1800_dpbrdg: regulator-1v8-dpbrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_dpbrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1800_dpbrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 126 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6359_vio18_ldo_reg>; + }; + /* system wide LDO 1.8V power rail */ pp1800_ldo_g: regulator-1v8-g { compatible =3D "regulator-fixed"; @@ -34,6 +71,28 @@ pp1800_ldo_g: regulator-1v8-g { vin-supply =3D <&pp3300_g>; }; =20 + pp1800_mipibrdg: regulator-1v8-mipibrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_mipibrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1800_mipibrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 128 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6359_vio18_ldo_reg>; + }; + + pp3300_dpbrdg: regulator-3v3-dpbrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_dpbrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp3300_dpbrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 26 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp3300_g>; + }; + /* system wide switching 3.3V power rail */ pp3300_g: regulator-3v3-g { compatible =3D "regulator-fixed"; @@ -56,6 +115,17 @@ pp3300_ldo_z: regulator-3v3-z { vin-supply =3D <&ppvar_sys>; }; =20 + pp3300_mipibrdg: regulator-3v3-mipibrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_mipibrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp3300_mipibrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 127 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp3300_g>; + }; + /* separately switched 3.3V power rail */ pp3300_u: regulator-3v3-u { compatible =3D "regulator-fixed"; @@ -719,6 +789,48 @@ pins-wifi-kill { }; }; =20 + pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + + pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { + pins-en { + pinmux =3D ; + output-low; + }; + }; + pp3300_wlan_pins: pp3300-wlan-pins { pins-pcie-en-pp3300-wlan { pinmux =3D ; --=20 2.38.1 From nobody Sat Sep 21 09:30:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25522C4332F for ; Wed, 2 Nov 2022 19:06:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230106AbiKBTGh (ORCPT ); Wed, 2 Nov 2022 15:06:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231761AbiKBTG0 (ORCPT ); Wed, 2 Nov 2022 15:06:26 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B00A8C4D; Wed, 2 Nov 2022 12:06:25 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 19A4366028F8; Wed, 2 Nov 2022 19:06:23 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667415984; bh=cAWS2o7ezo8lcFTLvtHcfgbNs2i5XRzG1MatYzmAa7k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PG6t0H5cZwbo4xAkZShlrqbnZL965LVlR0PxoTqsItZVoxk392J3IfLeTwAR2CUBa oW87ZVKbApzTsorMEeKZ+frpqCI/dhiUzqosZU7yjd/VVfdX6XEp7hNzj1QTmuOuFw N/SLnt4MC244GyHTMFkq+sbuTCAzTtSsgBgWJsMKQtzwemJVfe5V6tVvNVk6W4REWR /e8a7AwBxNKFaNGuuMqirgaLtbdyKOn2iQInzq0Y03umd4TPduhnvdnMw5rl4R4p1p W/d4TgHvZCa1hOt1hfZaOyC6HQCvGlXi4oeDICIbV1EY4rWTX4DIvjrtCfki+zNss9 acIOQT9ZOYtSg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 2/5] arm64: dts: mediatek: asurada: Add display backlight Date: Wed, 2 Nov 2022 15:06:08 -0400 Message-Id: <20221102190611.283546-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221102190611.283546-1-nfraprado@collabora.com> References: <20221102190611.283546-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the display backlight for the Asurada platform. It relies on the display PWM controller, so also enable and configure this component. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Signed-off-by: N=C3=ADcolas F. R. A. Prado --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index fafca7428539..666021ca4d4f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -23,6 +23,16 @@ memory@40000000 { reg =3D <0 0x40000000 0 0x80000000>; }; =20 + backlight_lcd0: backlight-lcd0 { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm0 0 500000>; + power-supply =3D <&ppvar_sys>; + enable-gpios =3D <&pio 152 0>; + brightness-levels =3D <0 1023>; + num-interpolated-steps =3D <1023>; + default-brightness-level =3D <576>; + }; + pp1000_dpbrdg: regulator-1v0-dpbrdg { compatible =3D "regulator-fixed"; regulator-name =3D "pp1000_dpbrdg"; @@ -838,6 +848,17 @@ pins-pcie-en-pp3300-wlan { }; }; =20 + pwm0_pins: pwm0-default-pins { + pins-pwm { + pinmux =3D ; + }; + + pins-inhibit { + pinmux =3D ; + output-high; + }; + }; + scp_pins: scp-pins { pins-vreq-vao { pinmux =3D ; @@ -899,6 +920,13 @@ &pmic { interrupts-extended =3D <&pio 214 IRQ_TYPE_LEVEL_HIGH>; }; =20 +&pwm0 { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm0_pins>; +}; + &scp { status =3D "okay"; =20 --=20 2.38.1 From nobody Sat Sep 21 09:30:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 735A6C4332F for ; Wed, 2 Nov 2022 19:06:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231774AbiKBTGl (ORCPT ); Wed, 2 Nov 2022 15:06:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231791AbiKBTG1 (ORCPT ); Wed, 2 Nov 2022 15:06:27 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2396EC00; Wed, 2 Nov 2022 12:06:27 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id A1F6A66028C5; Wed, 2 Nov 2022 19:06:24 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667415985; bh=TnVNIWSbSWEvlbCLuZhMaEZgW/k9jezqptAq9ChuQVw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RogDAN2ADhgHGvOQmXzG/+BOGYKMiUMTmAHqgUQ81jkihxJQDBH8JRbkFvZMmxSvv WLw34Hzwa++X6mnO3O5ZkYdFC0bG391Hlbgxa5p7ZwdVkgGKu3uZX3W3eQTuZYVztU lNKzaPSC+PBu3Cb47VKscs3wlFi0AKWNw5UayP+uSJojOY+y2y38zKLWcEUgBoGoPU tc7nZxWNlyWj9WNPF5llT9xmVUAUq3aXwFt2l9w4Ca5aI91k7KiMR/4ukcoQEO8blL dAg0pKTnhGBymQBmhdHuNMBBCQToCh414DDU7jxJVOhqXTY7ZHwJDrrx+4nO/ASc8q RBhKqucVFsBFw== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 3/5] arm64: dts: mediatek: asurada: Enable internal display Date: Wed, 2 Nov 2022 15:06:09 -0400 Message-Id: <20221102190611.283546-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221102190611.283546-1-nfraprado@collabora.com> References: <20221102190611.283546-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The asurada platform has an ANX7625 bridge connecting the DSI's output to the internal eDP panel. Add and enable these devices in order to get a usable internal display. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Signed-off-by: N=C3=ADcolas F. R. A. Prado --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 666021ca4d4f..ace44827de17 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -198,6 +198,14 @@ wifi_restricted_dma_region: wifi@c0000000 { }; }; =20 +&dsi0 { + status =3D "okay"; +}; + +&dsi_out { + remote-endpoint =3D <&anx7625_in>; +}; + &i2c0 { status =3D "okay"; =20 @@ -246,6 +254,53 @@ &i2c3 { clock-frequency =3D <400000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c3_pins>; + + anx_bridge: anx7625@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&anx7625_pins>; + enable-gpios =3D <&pio 41 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&pio 42 GPIO_ACTIVE_HIGH>; + vdd10-supply =3D <&pp1000_mipibrdg>; + vdd18-supply =3D <&pp1800_mipibrdg>; + vdd33-supply =3D <&pp3300_mipibrdg>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + anx7625_in: endpoint { + remote-endpoint =3D <&dsi_out>; + }; + }; + + port@1 { + reg =3D <1>; + + anx7625_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible =3D "edp-panel"; + power-supply =3D <&pp3300_mipibrdg>; + backlight =3D <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&anx7625_out>; + }; + }; + }; + }; + }; }; =20 &i2c7 { @@ -256,6 +311,10 @@ &i2c7 { pinctrl-0 =3D <&i2c7_pins>; }; =20 +&mipi_tx0 { + status =3D "okay"; +}; + &mmc0 { status =3D "okay"; =20 @@ -587,6 +646,20 @@ &pio { "AUD_DAT_MISO0", "AUD_DAT_MISO1"; =20 + anx7625_pins: anx7625-default-pins { + pins-out { + pinmux =3D , + ; + output-low; + }; + + pins-in { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; + cr50_int: cr50-irq-default-pins { pins-gsc-ap-int-odl { pinmux =3D ; --=20 2.38.1 From nobody Sat Sep 21 09:30:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3E98C433FE for ; Wed, 2 Nov 2022 19:06:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231359AbiKBTGq (ORCPT ); Wed, 2 Nov 2022 15:06:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231806AbiKBTGf (ORCPT ); Wed, 2 Nov 2022 15:06:35 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4AE1C4D; Wed, 2 Nov 2022 12:06:28 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 385B66602925; Wed, 2 Nov 2022 19:06:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667415987; bh=JbceIHQ4cbd/hM7hvtkZ242gzHvZFAdS9o8A6QVpvLQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lXhLqga2q1eMBpIWij9vfppHslbMQ+wjjsZJLv6zkl2VZtdngFR3PFMZdSGWUe0Xy Ohx5OYv0kwdJ/ZYBQjh3+GifliqABHnGdt05/6SyxV/2hswDnwdJzw7xWMlpW22RW0 ZtiaShhcq3A/6hBQEcI8xcznZU1QWXeSBJrQgrj5gJrb+MpQpyNKRemeGNchewSdSB 2dUzBvnd8XbnSgCjmpmTyNUVQjcQtxZHw4SiupGqza1Sir87NK5B8NYi5TVm8tKiTI F6MlaiPQTfnbTKb6NgI94woJQCgbiQRjpC33dZGRcX1JI44bJGlo5y0USRELQVDSJc wb5OcUc0W9jDQ== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 4/5] arm64: dts: mediatek: asurada: Enable audio support Date: Wed, 2 Nov 2022 15:06:10 -0400 Message-Id: <20221102190611.283546-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221102190611.283546-1-nfraprado@collabora.com> References: <20221102190611.283546-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable audio support for the Asurada platform. This consists of the machine sound card, the rt1015p codec for the speakers, the rt5682 codec for the headset, and the dmic codec for the internal microphone. Newer revisions of spherion and hayato use the rt5682s codec for the headset instead, so the codecs and card compatible are added through separate dtsi files to prepare for that. HDMI audio support is left out for now since the DisplayPort chip required isn't enabled yet. Tested-by: Chen-Yu Tsai Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- Changes in v3: - Moved rt5682, rt1015p and sound card compatible to separate dtsi files to prepare for future revisions using different codecs - Made node names generic for rt5682, rt1015p and sound card - Set sound-dai-cells to 1 for rt5682 - Added DBVDD and LDO1-IN supplies for rt5682 Changes in v2: - Added this commit .../mt8192-asurada-audio-rt1015p-rt5682.dtsi | 19 ++ .../mt8192-asurada-audio-rt1015p.dtsi | 26 ++ .../mediatek/mt8192-asurada-audio-rt5682.dtsi | 21 ++ .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 1 + .../mediatek/mt8192-asurada-spherion-r0.dts | 1 + .../boot/dts/mediatek/mt8192-asurada.dtsi | 245 ++++++++++++++++++ 6 files changed, 313 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt101= 5p-rt5682.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt101= 5p.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt568= 2.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt56= 82.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.= dtsi new file mode 100644 index 000000000000..f521f50d448f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + */ + +#include "mt8192-asurada-audio-rt5682.dtsi" +#include "mt8192-asurada-audio-rt1015p.dtsi" + +&sound { + compatible =3D "mediatek,mt8192_mt6359_rt1015p_rt5682"; + + speaker-codecs { + sound-dai =3D <&rt1015p>; + }; + + headset-codec { + sound-dai =3D <&rt5682 0>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi= b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi new file mode 100644 index 000000000000..e5743789934e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ + +#include +#include + +/ { + rt1015p: audio-codec { + compatible =3D "realtek,rt1015p"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rt1015p_pins>; + sdb-gpios =3D <&pio 147 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <0>; + }; +}; + +&pio { + rt1015p_pins: rt1015p-default-pins { + pins { + pinmux =3D ; + output-low; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi = b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi new file mode 100644 index 000000000000..05e48b870a92 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ + +&i2c1 { + rt5682: audio-codec@1a { + compatible =3D "realtek,rt5682i"; + reg =3D <0x1a>; + interrupts-extended =3D <&pio 18 IRQ_TYPE_LEVEL_LOW>; + realtek,jd-src =3D <1>; + realtek,btndet-delay =3D <16>; + #sound-dai-cells =3D <1>; + + AVDD-supply =3D <&mt6359_vio18_ldo_reg>; + DBVDD-supply =3D <&mt6359_vio18_ldo_reg>; + LDO1-IN-supply =3D <&mt6359_vio18_ldo_reg>; + MICVDD-supply =3D <&pp3300_g>; + VBAT-supply =3D <&pp3300_ldo_z>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/ar= ch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index 1e91491945f6..43a823990a92 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -4,6 +4,7 @@ */ /dts-v1/; #include "mt8192-asurada.dtsi" +#include "mt8192-asurada-audio-rt1015p-rt5682.dtsi" =20 / { model =3D "Google Hayato rev1"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/= arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index fa3d9573f37a..c6ad10cec95e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -4,6 +4,7 @@ */ /dts-v1/; #include "mt8192-asurada.dtsi" +#include "mt8192-asurada-audio-rt1015p-rt5682.dtsi" #include =20 / { diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index ace44827de17..ce9e43475f9e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -33,6 +33,12 @@ backlight_lcd0: backlight-lcd0 { default-brightness-level =3D <576>; }; =20 + dmic_codec: dmic-codec { + compatible =3D "dmic-codec"; + num-channels =3D <2>; + wakeup-delay-ms =3D <50>; + }; + pp1000_dpbrdg: regulator-1v0-dpbrdg { compatible =3D "regulator-fixed"; regulator-name =3D "pp1000_dpbrdg"; @@ -196,6 +202,62 @@ wifi_restricted_dma_region: wifi@c0000000 { reg =3D <0 0xc0000000 0 0x4000000>; }; }; + + sound: sound { + mediatek,platform =3D <&afe>; + pinctrl-names =3D "aud_clk_mosi_off", + "aud_clk_mosi_on", + "aud_dat_mosi_off", + "aud_dat_mosi_on", + "aud_dat_miso_off", + "aud_dat_miso_on", + "vow_dat_miso_off", + "vow_dat_miso_on", + "vow_clk_miso_off", + "vow_clk_miso_on", + "aud_nle_mosi_off", + "aud_nle_mosi_on", + "aud_dat_miso2_off", + "aud_dat_miso2_on", + "aud_gpio_i2s3_off", + "aud_gpio_i2s3_on", + "aud_gpio_i2s8_off", + "aud_gpio_i2s8_on", + "aud_gpio_i2s9_off", + "aud_gpio_i2s9_on", + "aud_dat_mosi_ch34_off", + "aud_dat_mosi_ch34_on", + "aud_dat_miso_ch34_off", + "aud_dat_miso_ch34_on", + "aud_gpio_tdm_off", + "aud_gpio_tdm_on"; + pinctrl-0 =3D <&aud_clk_mosi_off_pins>; + pinctrl-1 =3D <&aud_clk_mosi_on_pins>; + pinctrl-2 =3D <&aud_dat_mosi_off_pins>; + pinctrl-3 =3D <&aud_dat_mosi_on_pins>; + pinctrl-4 =3D <&aud_dat_miso_off_pins>; + pinctrl-5 =3D <&aud_dat_miso_on_pins>; + pinctrl-6 =3D <&vow_dat_miso_off_pins>; + pinctrl-7 =3D <&vow_dat_miso_on_pins>; + pinctrl-8 =3D <&vow_clk_miso_off_pins>; + pinctrl-9 =3D <&vow_clk_miso_on_pins>; + pinctrl-10 =3D <&aud_nle_mosi_off_pins>; + pinctrl-11 =3D <&aud_nle_mosi_on_pins>; + pinctrl-12 =3D <&aud_dat_miso2_off_pins>; + pinctrl-13 =3D <&aud_dat_miso2_on_pins>; + pinctrl-14 =3D <&aud_gpio_i2s3_off_pins>; + pinctrl-15 =3D <&aud_gpio_i2s3_on_pins>; + pinctrl-16 =3D <&aud_gpio_i2s8_off_pins>; + pinctrl-17 =3D <&aud_gpio_i2s8_on_pins>; + pinctrl-18 =3D <&aud_gpio_i2s9_off_pins>; + pinctrl-19 =3D <&aud_gpio_i2s9_on_pins>; + pinctrl-20 =3D <&aud_dat_mosi_ch34_off_pins>; + pinctrl-21 =3D <&aud_dat_mosi_ch34_on_pins>; + pinctrl-22 =3D <&aud_dat_miso_ch34_off_pins>; + pinctrl-23 =3D <&aud_dat_miso_ch34_on_pins>; + pinctrl-24 =3D <&aud_gpio_tdm_off_pins>; + pinctrl-25 =3D <&aud_gpio_tdm_on_pins>; + }; }; =20 &dsi0 { @@ -660,6 +722,165 @@ pins-in { }; }; =20 + aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { + pins-mosi-off { + pinmux =3D , + ; + }; + }; + + aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { + pins-mosi-on { + pinmux =3D , + ; + drive-strength =3D <10>; + }; + }; + + aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { + pins-miso-off { + pinmux =3D ; + }; + }; + + aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { + pins-miso-on { + pinmux =3D ; + }; + }; + + aud_dat_miso_off_pins: aud-dat-miso-off-pins { + pins-miso-off { + pinmux =3D , + ; + }; + }; + + aud_dat_miso_on_pins: aud-dat-miso-on-pins { + pins-miso-on { + pinmux =3D , + ; + drive-strength =3D <10>; + }; + }; + + aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { + pins-miso-off { + pinmux =3D ; + }; + }; + + aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { + pins-miso-on { + pinmux =3D ; + }; + }; + + aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { + pins-mosi-off { + pinmux =3D ; + }; + }; + + aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { + pins-mosi-on { + pinmux =3D ; + }; + }; + + aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { + pins-mosi-off { + pinmux =3D , + ; + }; + }; + + aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { + pins-mosi-on { + pinmux =3D , + ; + drive-strength =3D <10>; + }; + }; + + aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { + pins-i2s3-off { + pinmux =3D , + , + ; + }; + }; + + aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { + pins-i2s3-on { + pinmux =3D , + , + ; + }; + }; + + aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { + pins-i2s8-off { + pinmux =3D , + , + , + ; + }; + }; + + aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { + pins-i2s8-on { + pinmux =3D , + , + , + ; + }; + }; + + aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { + pins-i2s9-off { + pinmux =3D ; + }; + }; + + aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { + pins-i2s9-on { + pinmux =3D ; + }; + }; + + aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { + pins-tdm-off { + pinmux =3D , + , + , + ; + }; + }; + + aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { + pins-tdm-on { + pinmux =3D , + , + , + ; + }; + }; + + aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { + pins-nle-mosi-off { + pinmux =3D , + ; + }; + }; + + aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { + pins-nle-mosi-on { + pinmux =3D , + ; + }; + }; + cr50_int: cr50-irq-default-pins { pins-gsc-ap-int-odl { pinmux =3D ; @@ -987,6 +1208,30 @@ pins-report-sw { output-low; }; }; + + vow_clk_miso_off_pins: vow-clk-miso-off-pins { + pins-miso-off { + pinmux =3D ; + }; + }; + + vow_clk_miso_on_pins: vow-clk-miso-on-pins { + pins-miso-on { + pinmux =3D ; + }; + }; + + vow_dat_miso_off_pins: vow-dat-miso-off-pins { + pins-miso-off { + pinmux =3D ; + }; + }; + + vow_dat_miso_on_pins: vow-dat-miso-on-pins { + pins-miso-on { + pinmux =3D ; + }; + }; }; =20 &pmic { --=20 2.38.1 From nobody Sat Sep 21 09:30:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23826C4332F for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1667415989; bh=psNsBgRZUfl25MmyYsegtoE6p8qBYKvjuaAigeczHcs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BzUZx3QI5rk9bRKJ/8KzAxkEVIXNJ+QBKyG0LMVSOyppAkTPIVMdu6NXv5wMN8oNo 4AlA3dZhpmeLUggTxnViPoZTn9mD0lydKzTacl/XHLlArSbkxB8EuV5xyjuB6NgXf0 1kUO1NR7iGdyuep8Kct9VqnrJMq3CDW+InY8tWOLJ+XmTEAZBAWiLdatnFUtLfpwr/ 2gfDkryv8KWwn6Tyxg7hf3gOgoXh+3pvclEQrUl0gA4fljUi/oaPQca2B/7aIwrDhY kr7YB7ZVMEk1PnQK6d5aqy22IftEu0y/eJMrdWSpiZDSHHvhCiXU5WRKfZG7lwt/ox NWPNl0xlr28Bg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 5/5] arm64: dts: mediatek: asurada: Add aliases for i2c and mmc Date: Wed, 2 Nov 2022 15:06:11 -0400 Message-Id: <20221102190611.283546-6-nfraprado@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221102190611.283546-1-nfraprado@collabora.com> References: <20221102190611.283546-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add aliases for the i2c and mmc nodes on the Asurada platform DT to ensure that we get stable ids for those devices on userspace. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: N=C3=ADcolas F. R. A. Prado --- Changes in v3: - Removed i2c4, 5, 6, 8 and 9 as they aren't used on asurada Changes in v2: - Added this commit arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index ce9e43475f9e..9f12257ab4e7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -11,6 +11,13 @@ =20 / { aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c7 =3D &i2c7; + mmc0 =3D &mmc0; + mmc1 =3D &mmc1; serial0 =3D &uart0; }; =20 --=20 2.38.1