From nobody Thu Apr 9 04:44:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A252BC43219 for ; Wed, 2 Nov 2022 09:09:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231298AbiKBJJe (ORCPT ); Wed, 2 Nov 2022 05:09:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230311AbiKBJIv (ORCPT ); Wed, 2 Nov 2022 05:08:51 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AAE027FED for ; Wed, 2 Nov 2022 02:08:49 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id b5so15703674pgb.6 for ; Wed, 02 Nov 2022 02:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cWX3PFtX+iNvvcqKHYXPbN+3ItiEZ3sX7UGhc0uTyP8=; b=QwqjzGJgppdayDXTm6UjIfNJI4qwy9hl2hsoOCOlR9hemvSkrVEKJVWHqSpRHEyAu7 eQbTjEbZCGUK4OPFtRYcs7X/y6nQh3e2mAA4zpGMKvQO2cldA2MczhIiJLJZN6bInIhh HuOgvT0jecYqJ+0ltQ9vdeweX9z+FEfSLDJt9VP+z7sPrbru9R2qt/qQNEUHCE9NCepm mfdBEu1YTE9IwsdbAK0Xio1y+1S/2HBBiIWYIlnbLzS76dGG40lmEznyXPRynn92y0dz bbdvGHpe2EMxZ9VYHD7lPoz8SIWXdD16xJeLt6Vsm9FLoXaQu+KeLhXfee2cC5nZB6PY Z0fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cWX3PFtX+iNvvcqKHYXPbN+3ItiEZ3sX7UGhc0uTyP8=; b=gakeFxsRP7hLuZ/Hh/NHU0AnDayPHEmOUZXv5WMro+AHqNE3WjWB+yWeJZuHo2kYzm L2bYfQjwgfVHnXHdTnnyrTCRr42ILuXJ9nn5v+K5iVxtpA0nyPK613awIBOK1m+XRx2W MOLygMrsA6Ph15c5moZHCV7bLSy+mtjp8vONzwHZcIgs11IvB8bYTdLmBIYNWjsiV4yZ XHa0dhEKEfqq2Rbk6XOkp1iTdBs1/djtKc17SwzjTAH/WwNwPLhf8KAKb4sKCbt9usfT d2JIsqRKpvEAkvayLLCBjwIV4+J7oiFb66hZRIBKECvFznDlvReLv+NE94u5dtfw/4KA NJ5g== X-Gm-Message-State: ACrzQf0w1XWErMRG45rwS7Tyq1dH9deOfnSxO54zkmNj5Xko9T4Hg2EZ i5LiTULa1zGWyg2dyRkPVYn9 X-Google-Smtp-Source: AMsMyM7WN7H5q2WXhID5u3tLTwQgGgRaR6i8jg93NwvaEumnfLJJNhboz0orIs4S+pGTqV+bgQ2Qjg== X-Received: by 2002:a05:6a00:2906:b0:52a:bc7f:f801 with SMTP id cg6-20020a056a00290600b0052abc7ff801mr24444615pfb.49.1667380128742; Wed, 02 Nov 2022 02:08:48 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.178]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b0017f36638010sm7856126plg.276.2022.11.02.02.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 02:08:47 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v4 2/3] arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs Date: Wed, 2 Nov 2022 14:38:17 +0530 Message-Id: <20221102090818.65321-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102090818.65321-1-manivannan.sadhasivam@linaro.org> References: <20221102090818.65321-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index d32f08df743d..234d2722a4fa 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -51,6 +51,7 @@ CPU0: cpu@0 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -70,6 +71,7 @@ CPU1: cpu@100 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -86,6 +88,7 @@ CPU2: cpu@200 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -102,6 +105,7 @@ CPU3: cpu@300 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -118,6 +122,7 @@ CPU4: cpu@400 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -134,6 +139,7 @@ CPU5: cpu@500 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -151,6 +157,7 @@ CPU6: cpu@600 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -167,6 +174,7 @@ CPU7: cpu@700 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 2>; L2_700: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -3075,6 +3083,7 @@ cpufreq_hw: cpufreq@17d91000 { ; interrupt-names =3D "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; }; =20 gem_noc: interconnect@19100000 { --=20 2.25.1