From nobody Thu Apr 9 04:44:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B53C433FE for ; Wed, 2 Nov 2022 09:09:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230258AbiKBJJO (ORCPT ); Wed, 2 Nov 2022 05:09:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230209AbiKBJIp (ORCPT ); Wed, 2 Nov 2022 05:08:45 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F2FC2715D for ; Wed, 2 Nov 2022 02:08:44 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id q1-20020a17090a750100b002139ec1e999so1357040pjk.1 for ; Wed, 02 Nov 2022 02:08:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qLmIT2EuV7uL5/q+fGUeI0QcACFtgGdUnQVYaLsbI/Y=; b=b7nHLBjUufJmJspBXuHAtSMK8Px+kXryq+x/CMQKjqzJI2+omB03MHFs+b0SIgt+FP ZdI9759K2BCORPFtvXQdMtpc7IxupthgKO/LLlXMIOTEYROvYWiWw0StCpvH/mhM8Mcj YlEvEISlkDng044eoQKPXbhgB97MEu1aDcD6XzEGWn7w5jmthW6qRH7OZKWxKE1CHMmX jtbXxrxI/q/jtp22fzbcXb0FV6V5RQL7cqFeZUvm0cFzE0ojgPwh/lyLrC0KL20rDyv9 i860opxDSZ14AaF2DBg0DXUMUSrnuSYFSHN5AOFPVGBL6wVOXTqsTFXmoTI+ikEv4epo n+Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qLmIT2EuV7uL5/q+fGUeI0QcACFtgGdUnQVYaLsbI/Y=; b=vB4W8InefUY2oUca9G2uM9psK6M5PxeeY1nGLNWipzZ5JyQXnXdwPzJs1AGZcPrYE5 RBuNIDjK3FfVLMrsBP0oI8RSuKqglqE4gYsw4Y3GKXKP0y2mdxPMu6Flg55+GTmA1n8H mVIb82dlGAD6jQ+PnNd/JnOi4PCIg3Yb/yjBdFgT/zD5eYCiovQPt98r0OpEVG4xL/BK 5a1YOo8Sm5x4o4Pr/cjNKL46z/sTlKgayYntof+YnLwJWbZxtluiahSEegmU6osm1VJi MWW0rfsE1zi5tahaooGY6oSjvtckCcrq1s799+RLuGdqBqVh3/HyGQhxubJklPZ6exRa eZ3A== X-Gm-Message-State: ACrzQf1GaDiUozGzvE7hLyIENb5VNVFy0MDqHPYx6karOpkJwLJXiRjo Cw1bPKY8dP3kxy80Q4xcDRu5 X-Google-Smtp-Source: AMsMyM77JnAlbEFTQqEbo4jyfDXA5M0vK+5KthBYKkmJ2++rlrrrtMRLZIKj6FZbIvnLIGRIeggJQw== X-Received: by 2002:a17:90a:cb8c:b0:212:eba5:a143 with SMTP id a12-20020a17090acb8c00b00212eba5a143mr24629236pju.79.1667380123644; Wed, 02 Nov 2022 02:08:43 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.178]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b0017f36638010sm7856126plg.276.2022.11.02.02.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 02:08:42 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v4 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider Date: Wed, 2 Nov 2022 14:38:16 +0530 Message-Id: <20221102090818.65321-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102090818.65321-1-manivannan.sadhasivam@linaro.org> References: <20221102090818.65321-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 24fa3d87a40b..9ac8ad5b71b5 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -56,6 +56,9 @@ properties: '#freq-domain-cells': const: 1 =20 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -83,6 +86,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -99,6 +103,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -112,6 +117,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -125,6 +131,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -138,6 +145,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -151,6 +159,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -164,6 +173,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -177,6 +187,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_700: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -197,6 +208,7 @@ examples: clock-names =3D "xo", "alternate"; =20 #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; }; }; ... --=20 2.25.1