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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id bd26-20020a05600c1f1a00b003cf6c2f9513sm1425322wmb.2.2022.11.02.02.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 02:01:51 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v2 4/5] clk: qcom: dispcc-sm8250: Add missing EDP clocks for sm8350 Date: Wed, 2 Nov 2022 10:01:39 +0100 Message-Id: <20221102090140.965450-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102090140.965450-1-robert.foss@linaro.org> References: <20221102090140.965450-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SM8350 supports embedded displayport, but the clocks for this were previously not accounted for. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8= 250.c index a7606580cf22..d2aaa44ed3d4 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -462,6 +462,20 @@ static struct clk_branch disp_cc_mdss_edp_link_clk =3D= { }, }; =20 +static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src =3D { + .reg =3D 0x2288, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "disp_cc_mdss_edp_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + static struct clk_branch disp_cc_mdss_edp_link_intf_clk =3D { .halt_reg =3D 0x2074, .halt_check =3D BRANCH_HALT, @@ -471,7 +485,7 @@ static struct clk_branch disp_cc_mdss_edp_link_intf_clk= =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "disp_cc_mdss_edp_link_intf_clk", .parent_hws =3D (const struct clk_hw*[]){ - &disp_cc_mdss_edp_link_clk_src.clkr.hw, + &disp_cc_mdss_edp_link_div_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_GET_RATE_NOCACHE, @@ -1175,6 +1189,7 @@ static struct clk_regmap *disp_cc_sm8250_clocks[] =3D= { [DISP_CC_MDSS_EDP_GTC_CLK_SRC] =3D &disp_cc_mdss_edp_gtc_clk_src.clkr, [DISP_CC_MDSS_EDP_LINK_CLK] =3D &disp_cc_mdss_edp_link_clk.clkr, [DISP_CC_MDSS_EDP_LINK_CLK_SRC] =3D &disp_cc_mdss_edp_link_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_edp_link_div_clk_sr= c.clkr, [DISP_CC_MDSS_EDP_LINK_INTF_CLK] =3D &disp_cc_mdss_edp_link_intf_clk.clkr, [DISP_CC_MDSS_EDP_PIXEL_CLK] =3D &disp_cc_mdss_edp_pixel_clk.clkr, [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] =3D &disp_cc_mdss_edp_pixel_clk_src.clkr, @@ -1285,7 +1300,11 @@ static int disp_cc_sm8250_probe(struct platform_devi= ce *pdev) &disp_cc_mdss_dp_pixel1_clk_src, &disp_cc_mdss_dp_pixel2_clk_src, &disp_cc_mdss_dp_pixel_clk_src, + &disp_cc_mdss_edp_aux_clk_src, + &disp_cc_mdss_edp_link_clk_src, + &disp_cc_mdss_edp_pixel_clk_src, &disp_cc_mdss_esc0_clk_src, + &disp_cc_mdss_esc1_clk_src, &disp_cc_mdss_mdp_clk_src, &disp_cc_mdss_pclk0_clk_src, &disp_cc_mdss_pclk1_clk_src, @@ -1297,6 +1316,7 @@ static int disp_cc_sm8250_probe(struct platform_devic= e *pdev) &disp_cc_mdss_byte1_div_clk_src, &disp_cc_mdss_dp_link1_div_clk_src, &disp_cc_mdss_dp_link_div_clk_src, + &disp_cc_mdss_edp_link_div_clk_src, }; unsigned int i; static bool offset_applied; --=20 2.34.1