From nobody Thu Apr 9 03:15:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D918AC4332F for ; Wed, 2 Nov 2022 08:38:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230462AbiKBIiW (ORCPT ); Wed, 2 Nov 2022 04:38:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230440AbiKBIiO (ORCPT ); Wed, 2 Nov 2022 04:38:14 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C2C824F25 for ; Wed, 2 Nov 2022 01:38:13 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id l2so15885651pld.13 for ; Wed, 02 Nov 2022 01:38:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jQnAjVM8KfWMqcwU3yG9m91ABhfRemXy71C0Mul10HU=; b=BI5z3t5yh+o/6QROXQ6AMqcln1aDKa4g86WvBaWv08SoJh/CN4rpQJxusRiuGqubs3 0WKp/NDTUz2/m4GvxtOKJybTLZBtjcCpjj2xkSoaqzwHfLROyh4mIRqDiuEPWkeSsBJz mJ0WEEO7xVScBm9QejSv5iKbaDFRPnEY+LhjOrEGX4V9nOd91nFhC95M0GNBinOthfQA bdH9/BADrpnxUJTwYvjk2RDtf+NFSc3pPYzZs48nYMYxMoj+2vXn6IY4Yb39O1nt+p9A tr6pOV3jUfPvwEL2quP5wv98BXGLmipv9MQoUzIWqMTRMMEMsGTJcY8Ysrf5YeuUYfB+ tdCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jQnAjVM8KfWMqcwU3yG9m91ABhfRemXy71C0Mul10HU=; b=G4xY9r1x4UjPKrFUGMiOF8vSe2jadVf8wB8o3d9bwTonoDvSnNYDF/pTJLEO9VAgZ+ bf3AxrpSnxVeM6F/YaOBb12BjuzPHgW8hNiMD36wz1BhA4R5YhrYq9zIC21CMPbG8uM/ XCX28gdvEAo0zAYo6WFuSz3lkZd7F0GcabDRMT0FurDYv8tOd0mcj6XUi0yT0N7kN32C Ya7LSGHybYi3GygWuO/D33COI8fdhXvIdNvF41iNK8GEWlYCNES4WhHNGMurpV7Dwc6p V15GDhP4LMc2C/qzwjhoEBoK4uhx9dr/eWylCAL4ERLDwcjDKiKtYPy2iovMw4zjNKyF 8lLw== X-Gm-Message-State: ACrzQf0sv/UQHh5eKl82EDMHaV8pgCEOuUA13EwkfaWA7SgsKIsYIwn7 AOiq4wthPa0xWzTSyKnIOHEs X-Google-Smtp-Source: AMsMyM77dg5YxTTvjtwAYBd+pJTnRDwtud450+37wTGwfMoZBBFV0IUkYDuLrrWRee0lywU00ZFaSw== X-Received: by 2002:a17:90b:1bc1:b0:213:e2af:b1f4 with SMTP id oa1-20020a17090b1bc100b00213e2afb1f4mr15165846pjb.47.1667378292730; Wed, 02 Nov 2022 01:38:12 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.178]) by smtp.gmail.com with ESMTPSA id x19-20020aa79573000000b0056bcb102e7bsm7887770pfq.68.2022.11.02.01.38.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 01:38:11 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v3 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider Date: Wed, 2 Nov 2022 14:07:49 +0530 Message-Id: <20221102083751.56330-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102083751.56330-1-manivannan.sadhasivam@linaro.org> References: <20221102083751.56330-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index cbba8979fe0e..2e0336163ffb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -57,6 +57,9 @@ properties: '#freq-domain-cells': const: 1 =20 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -84,6 +87,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -100,6 +104,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -113,6 +118,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -126,6 +132,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -139,6 +146,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -152,6 +160,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -165,6 +174,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -178,6 +188,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_700: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -198,6 +209,7 @@ examples: clock-names =3D "xo", "alternate"; =20 #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; }; }; ... --=20 2.25.1 From nobody Thu Apr 9 03:15:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE455C4332F for ; Wed, 2 Nov 2022 08:38:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230494AbiKBIia (ORCPT ); Wed, 2 Nov 2022 04:38:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230440AbiKBIi1 (ORCPT ); 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Wed, 02 Nov 2022 01:38:17 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 2/3] arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs Date: Wed, 2 Nov 2022 14:07:50 +0530 Message-Id: <20221102083751.56330-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102083751.56330-1-manivannan.sadhasivam@linaro.org> References: <20221102083751.56330-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 6c18cfca9a34..8f26cf9aad01 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -52,6 +52,7 @@ CPU0: cpu@0 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -71,6 +72,7 @@ CPU1: cpu@100 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -87,6 +89,7 @@ CPU2: cpu@200 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -103,6 +106,7 @@ CPU3: cpu@300 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -119,6 +123,7 @@ CPU4: cpu@400 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -135,6 +140,7 @@ CPU5: cpu@500 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -152,6 +158,7 @@ CPU6: cpu@600 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -168,6 +175,7 @@ CPU7: cpu@700 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; 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charset="utf-8" Qcom CPUFreq hardware (EPSS/OSM) controls clock and voltage to the CPU cores. But this relationship is not represented with the clk framework so far. So, let's make the qcom-cpufreq-hw driver a clock provider. This makes the clock producer/consumer relationship cleaner and is also useful for CPU related frameworks like OPP to know the frequency at which the CPUs are running. The clock frequency provided by the driver is for each frequency domain. We cannot get the frequency of each CPU core because, not all platforms support per-core DCVS feature. Also the frequency supplied by the driver is the actual frequency that comes out of the EPSS/OSM block after the DCVS operation. This frequency is not same as what the CPUFreq framework has set but it is the one that gets supplied to the CPUs after throttling by LMh. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index 76f840636828..b824f1bb04f4 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -53,6 +54,7 @@ struct qcom_cpufreq_data { bool cancel_throttle; struct delayed_work throttle_work; struct cpufreq_policy *policy; + struct clk_hw cpu_clk; =20 bool per_core_dcvs; }; @@ -601,8 +603,20 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = =3D { .ready =3D qcom_cpufreq_ready, }; =20 +static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsign= ed long parent_rate) +{ + struct qcom_cpufreq_data *data =3D container_of(hw, struct qcom_cpufreq_d= ata, cpu_clk); + + return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ; +} + +static const struct clk_ops qcom_cpufreq_hw_clk_ops =3D { + .recalc_rate =3D qcom_cpufreq_hw_recalc_rate, +}; + static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct clk_hw_onecell_data *clk_data; struct device *dev =3D &pdev->dev; struct device *cpu_dev; struct clk *clk; @@ -645,8 +659,16 @@ static int qcom_cpufreq_hw_driver_probe(struct platfor= m_device *pdev) =20 qcom_cpufreq.soc_data =3D of_device_get_match_data(dev); =20 + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, num_domains), G= FP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num =3D num_domains; + for (i =3D 0; i < num_domains; i++) { struct qcom_cpufreq_data *data =3D &qcom_cpufreq.data[i]; + struct clk_init_data init =3D {}; + const char *clk_name; struct resource *res; void __iomem *base; =20 @@ -658,6 +680,27 @@ static int qcom_cpufreq_hw_driver_probe(struct platfor= m_device *pdev) =20 data->base =3D base; data->res =3D res; + + /* Register CPU clock for each frequency domain */ + clk_name =3D devm_kasprintf(dev, GFP_KERNEL, "qcom_cpufreq%d", i); + init.name =3D clk_name; + init.flags =3D CLK_GET_RATE_NOCACHE; + init.ops =3D &qcom_cpufreq_hw_clk_ops; + data->cpu_clk.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &data->cpu_clk); + if (ret < 0) { + dev_err(dev, "Failed to register Qcom CPUFreq clock\n"); + return ret; + } + + clk_data->hws[i] =3D &data->cpu_clk; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret < 0) { + dev_err(dev, "Failed to add Qcom CPUFreq clock provider\n"); + return ret; } =20 ret =3D cpufreq_register_driver(&cpufreq_qcom_hw_driver); --=20 2.25.1