From nobody Thu Apr 9 01:42:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB56EC43217 for ; Tue, 1 Nov 2022 21:59:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231217AbiKAV7A (ORCPT ); Tue, 1 Nov 2022 17:59:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230473AbiKAV6e (ORCPT ); Tue, 1 Nov 2022 17:58:34 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C02E86316; Tue, 1 Nov 2022 14:58:29 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw6G5131024; Tue, 1 Nov 2022 16:58:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667339886; bh=ddqZDV3FJMUZFdWZvWshIsmQROUH4N1pUkz1Jj/sBKg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WRfOCJv9wYH43g/6w8SXnr8P34gVuLT/4CazqgkcPCbn9DcuUObdATE/mW0aVbw2d iAPFvjgd67HktMA9qkEWHHQhwaTUsdrOF2sfKYu2v0NN3jG3LTBYXop/ereBC6PsIX //z9aQ6WxTgH/S6EbtnQn2kEFrIboiB/x1jSG/Lo= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1Lw6r9021620 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 16:58:06 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 16:58:06 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 16:58:05 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44m117953; Tue, 1 Nov 2022 16:58:05 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 1/9] dt-bindings: mfd: Add TI-Nspire misc registers Date: Tue, 1 Nov 2022 16:57:56 -0500 Message-ID: <20221101215804.16262-2-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The TI Nspire devices contain a set of registers with a seemingly miscellaneous set of functionality. This area is known simply as the "misc" region. Signed-off-by: Andrew Davis --- .../bindings/mfd/ti,nspire-misc.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/ti,nspire-misc.ya= ml diff --git a/Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml b/Do= cumentation/devicetree/bindings/mfd/ti,nspire-misc.yaml new file mode 100644 index 0000000000000..d409eae7537bd --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,nspire-misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Nspire MISC hardware block + +maintainers: + - Andrew Davis + +description: | + System controller node represents a register region containing a set + of miscellaneous registers. The registers are not cohesive enough to + represent as any specific type of device. The typical use-case is + for some other node's driver, or platform-specific code, to acquire + a reference to the syscon node (e.g. by phandle, node path, or + search using a specific compatible value), interrogate the node (or + associated OS driver) to determine the location of the registers, + and access the registers directly. + +properties: + compatible: + items: + - enum: + - ti,nspire-misc + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + reboot: + $ref: "../power/reset/syscon-reboot.yaml" + +required: + - compatible + - reg + - reboot + +additionalProperties: false + +examples: + - | + misc: misc@900a0000 { + compatible =3D "ti,nspire-misc", "syscon", "simple-mfd"; + reg =3D <0x900a0000 0x1000>; + + reboot { + compatible =3D "syscon-reboot"; + offset =3D <0x08>; + value =3D <0x02>; + }; + }; --=20 2.37.3 From nobody Thu Apr 9 01:42:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 714ABC4332F for ; Tue, 1 Nov 2022 21:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230397AbiKAV6d (ORCPT ); Tue, 1 Nov 2022 17:58:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229717AbiKAV63 (ORCPT ); Tue, 1 Nov 2022 17:58:29 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A07033894; Tue, 1 Nov 2022 14:58:27 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw7fr128361; Tue, 1 Nov 2022 16:58:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667339887; bh=OOJwFcm19+ILowkx0sLyUoGCbhReDL1tZsy7vRQI/nk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tLID56y+RZVA5uAOJxc7m0j51YsfbBiK+9YhL+BIcROlqVjYUn+5sZnch1JULyooL u7LYfG/RlskahH1d0QmC9NF0EOwIVqQRs3negM/YufRabkRMHKwIkVwhVJtME/NY3Z jd4C1kBPu2KV7QjJBoG7FKuhSxuRyjvB0zMorOP4= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1Lw6Ro108283 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 16:58:06 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 16:58:06 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 16:58:06 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44n117953; Tue, 1 Nov 2022 16:58:06 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 2/9] ARM: dts: nspire: Use syscon-reboot to handle restart Date: Tue, 1 Nov 2022 16:57:57 -0500 Message-ID: <20221101215804.16262-3-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Writing this bit can be handled by the syscon-reboot driver. Add this node to DT. Signed-off-by: Andrew Davis Reviewed-by: Linus Walleij Tested-by: Fabian Vogt Reviewed-by: Fabian Vogt --- arch/arm/boot/dts/nspire.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index bb240e6a3a6f1..48fbc9d533c39 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -172,7 +172,14 @@ rtc: rtc@90090000 { }; =20 misc: misc@900a0000 { + compatible =3D "ti,nspire-misc", "syscon", "simple-mfd"; reg =3D <0x900a0000 0x1000>; + + reboot { + compatible =3D "syscon-reboot"; + offset =3D <0x08>; + value =3D <0x02>; + }; }; =20 pwr: pwr@900b0000 { --=20 2.37.3 From nobody Thu Apr 9 01:42:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F35EAC4332F for ; Tue, 1 Nov 2022 21:58:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230468AbiKAV6g (ORCPT ); Tue, 1 Nov 2022 17:58:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229648AbiKAV63 (ORCPT ); Tue, 1 Nov 2022 17:58:29 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13BC72BD9; Tue, 1 Nov 2022 14:58:26 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw70U128366; Tue, 1 Nov 2022 16:58:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667339887; bh=xz3MVvX826/jB7ymb5mYpupJ0Zh7v1aK1WyZn5W//P4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ndL0WpHHYafQEwIIRKtmaOgclvZrYc0LuQJzpOtitXAmAa/8sPoasdRhdNdulYsHG j2pQZ3E0RjSwtdxxFeKUW8/IKZ74t7cQgsffe2K+NW1vH5BJyOO50PkRHXoWHpAb2Z qsBbaNjqjKb1wWvtaCPmqPILga/fsEGbsGGu/S2o= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1Lw7Ve066657 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 16:58:07 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 16:58:07 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 16:58:07 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44o117953; Tue, 1 Nov 2022 16:58:06 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 3/9] ARM: dts: nspire: Fix cpu node to conform with DT binding Date: Tue, 1 Nov 2022 16:57:58 -0500 Message-ID: <20221101215804.16262-4-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This node does not follow the DT binding schema, correct this. Should result in no functional change. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/nspire.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index 48fbc9d533c39..cb72370515126 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -11,8 +11,13 @@ / { interrupt-parent =3D <&intc>; =20 cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu@0 { compatible =3D "arm,arm926ej-s"; + device_type =3D "cpu"; + reg =3D <0>; }; }; =20 --=20 2.37.3 From nobody Thu Apr 9 01:42:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E563BC433FE for ; Tue, 1 Nov 2022 21:58:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231139AbiKAV6n (ORCPT ); Tue, 1 Nov 2022 17:58:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230460AbiKAV6d (ORCPT ); Tue, 1 Nov 2022 17:58:33 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDDB62BEC; Tue, 1 Nov 2022 14:58:29 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw8jw114346; Tue, 1 Nov 2022 16:58:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667339888; bh=T/9FfSYIhjwx89Byw0qNaxKR8f3ko3kZtSGK9HYQOSM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mzGgR2GZDye6vrxrcGK7xfAFWpvD7tdpKeGfXTs3P5E49Kt5c8C0I3DElQTZPwn/6 OIXknt8Xj41oaVx+u0cI6oIWQTxq7Qrp+gsAhPvDH0AZW2jFZMEn7DxQqD2dSLOgKv ukQb9HrrgYjQNw5IzDonO54shALysx3FOv4k6g+w= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1Lw8lr095046 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 16:58:08 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 16:58:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 16:58:08 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44p117953; Tue, 1 Nov 2022 16:58:07 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 4/9] ARM: dts: nspire: Fix sram node to conform with DT binding Date: Tue, 1 Nov 2022 16:57:59 -0500 Message-ID: <20221101215804.16262-5-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This node does not follow the DT binding schema, correct this. Should result in no functional change. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/nspire.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index cb72370515126..f979b28e2576e 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -26,8 +26,15 @@ bootrom: bootrom@0 { }; =20 sram: sram@a4000000 { - device =3D "memory"; - reg =3D <0xa4000000 0x20000>; + compatible =3D "mmio-sram"; + reg =3D <0xa4000000 0x20000>; /* 128k */ + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0xa4000000 0x20000>; + + sram@0 { + reg =3D <0x0 0x20000>; + }; }; =20 timer_clk: timer_clk { --=20 2.37.3 From nobody Thu Apr 9 01:42:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E05CC4332F for ; Tue, 1 Nov 2022 21:58:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230518AbiKAV6k (ORCPT ); Tue, 1 Nov 2022 17:58:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229770AbiKAV63 (ORCPT ); Tue, 1 Nov 2022 17:58:29 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13D462BEC; Tue, 1 Nov 2022 14:58:26 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw94B128375; Tue, 1 Nov 2022 16:58:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667339889; bh=9iGeaCfyOTQ1lYkCvzgJTrNYgglzPhhVZxB8LG7f2UU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=U4j8rGtapgCmOkc3giaP4fWUTH5eNw/u49ZrvJ521eUHGn6WJXUlCUUogG/pm/MfV Sp9gEaSOnmMLySvkD1YOvOOGtkOk5Hqk2MD7i/9SrzPJ5jrGURb9IRQMON1BiCWBd8 GR8Gm7t3OpzOM1bvNENYReUFExYUrzFwVY6ktGDQ= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1Lw9lA066668 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 16:58:09 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 16:58:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 16:58:08 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44q117953; Tue, 1 Nov 2022 16:58:08 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 5/9] ARM: dts: nspire: Fix vbus_reg node to conform with DT binding Date: Tue, 1 Nov 2022 16:58:00 -0500 Message-ID: <20221101215804.16262-6-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This node does not follow the DT binding schema, correct this. All "regulator-fixed" are voltage type, so drop "regulator-type". Should result in no functional change. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/nspire.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index f979b28e2576e..9587e1ebeb931 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -71,7 +71,6 @@ vbus_reg: vbus_reg { compatible =3D "regulator-fixed"; =20 regulator-name =3D "USB VBUS output"; - regulator-type =3D "voltage"; =20 regulator-min-microvolt =3D <5000000>; regulator-max-microvolt =3D <5000000>; --=20 2.37.3 From nobody Thu Apr 9 01:42:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB32BC4332F for ; Tue, 1 Nov 2022 21:58:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231145AbiKAV6r (ORCPT ); Tue, 1 Nov 2022 17:58:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230456AbiKAV6d (ORCPT ); Tue, 1 Nov 2022 17:58:33 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDE3962E0; Tue, 1 Nov 2022 14:58:29 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw9gt078816; Tue, 1 Nov 2022 16:58:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667339889; bh=OUFC0xK0F4Q1H7mAWIMrUewcE+uKLkD6tdUD+imWtoA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X0ND3t+1I/1MIosbaCyBbGwVSCp0EAXtzCTaUFMuEPa030den65sIrfJuqQrlbhh9 drYdfMcluT5LEua+ZpkSKnv9xJkp1PGC8gM/mjJN9E5PW7gW8yqIOneq9XOu+A9/zY 2Iqdt+aV/z2b4N4/SbqM/yYr+Zt46wlQ8E7l8hgg= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1Lw9bC021665 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 16:58:09 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 16:58:09 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 16:58:09 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44r117953; Tue, 1 Nov 2022 16:58:08 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 6/9] ARM: dts: nspire: Fix uart node to conform with DT binding Date: Tue, 1 Nov 2022 16:58:01 -0500 Message-ID: <20221101215804.16262-7-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This node does not follow the DT binding schema, correct this. The arm,pl011 binding requires the first clock to be named "uartclk". Should result in no functional change. Signed-off-by: Andrew Davis Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/nspire-cx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.= dts index 590b7dff6ae50..837dbdd9af552 100644 --- a/arch/arm/boot/dts/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -24,7 +24,7 @@ &uart { compatible =3D "arm,pl011", "arm,primecell"; =20 clocks =3D <&uart_clk>, <&apb_pclk>; - clock-names =3D "uart_clk", "apb_pclk"; + clock-names =3D "uartclk", "apb_pclk"; }; =20 &timer0 { --=20 2.37.3 From nobody Thu Apr 9 01:42:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A054C4332F for ; Tue, 1 Nov 2022 21:59:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230501AbiKAV7E (ORCPT ); Tue, 1 Nov 2022 17:59:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230472AbiKAV6e (ORCPT ); Tue, 1 Nov 2022 17:58:34 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C077863C7; Tue, 1 Nov 2022 14:58:30 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1LwA3i131035; Tue, 1 Nov 2022 16:58:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667339890; bh=C800u3cMHjL+BUodN6e5x+czkE/u3vJ/9jfgZgxY6s4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EYQRhR7NmVSCw0wuw3VQpjnBM+Gmbfzfxv6nzt75DJRE20RP1Qg7IK2Gx/Ohb5aX8 ccKpqCAP06GjJY1KYDBt/up6P/RNgHOVBDXbjit78COTC0+uYnBZmudE2/UydQy9Hf PTqE8+QGGGC67IXmnrWtuierlvbMkDDTGBFIfA0M= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1LwACv108304 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 16:58:10 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 16:58:10 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 16:58:10 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44s117953; Tue, 1 Nov 2022 16:58:09 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 7/9] ARM: dts: nspire: Use MATRIX_KEY macro for linux,keymap Date: Tue, 1 Nov 2022 16:58:02 -0500 Message-ID: <20221101215804.16262-8-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This looks better and allows us to see the row and column numbers more easily. Switch to this macro here. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/nspire-clp.dts | 90 ++++++++++++++++++++++++-------- arch/arm/boot/dts/nspire-cx.dts | 90 ++++++++++++++++++++++++-------- arch/arm/boot/dts/nspire-tp.dts | 90 ++++++++++++++++++++++++-------- 3 files changed, 204 insertions(+), 66 deletions(-) diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-cl= p.dts index f52f38c615886..916ede0c2499c 100644 --- a/arch/arm/boot/dts/nspire-clp.dts +++ b/arch/arm/boot/dts/nspire-clp.dts @@ -6,32 +6,78 @@ */ /dts-v1/; =20 +#include + /include/ "nspire-classic.dtsi" =20 &keypad { linux,keymap =3D < - 0x0000001c 0x0001001c 0x00020039 - 0x0004002c 0x00050034 0x00060015 - 0x0007000b 0x0008002d 0x01000033 - 0x0101004e 0x01020011 0x01030004 - 0x0104002f 0x01050003 0x01060016 - 0x01070002 0x01080014 0x02000062 - 0x0201000c 0x0202001f 0x02030007 - 0x02040013 0x02050006 0x02060010 - 0x02070005 0x02080019 0x03000027 - 0x03010037 0x03020018 0x0303000a - 0x03040031 0x03050009 0x03060032 - 0x03070008 0x03080026 0x04000028 - 0x04010035 0x04020025 0x04040024 - 0x04060017 0x04080023 0x05000028 - 0x05020022 0x0503001b 0x05040021 - 0x0505001a 0x05060012 0x0507006f - 0x05080020 0x0509002a 0x0601001c - 0x0602002e 0x06030068 0x06040030 - 0x0605006d 0x0606001e 0x06070001 - 0x0608002b 0x0609000f 0x07000067 - 0x0702006a 0x0704006c 0x07060069 - 0x0707000e 0x0708001d 0x070a000d + MATRIX_KEY(0, 0, 0x1c) + MATRIX_KEY(0, 1, 0x1c) + MATRIX_KEY(0, 2, 0x39) + MATRIX_KEY(0, 4, 0x2c) + MATRIX_KEY(0, 5, 0x34) + MATRIX_KEY(0, 6, 0x15) + MATRIX_KEY(0, 7, 0x0b) + MATRIX_KEY(0, 8, 0x2d) + MATRIX_KEY(1, 0, 0x33) + MATRIX_KEY(1, 1, 0x4e) + MATRIX_KEY(1, 2, 0x11) + MATRIX_KEY(1, 3, 0x04) + MATRIX_KEY(1, 4, 0x2f) + MATRIX_KEY(1, 5, 0x03) + MATRIX_KEY(1, 6, 0x16) + MATRIX_KEY(1, 7, 0x02) + MATRIX_KEY(1, 8, 0x14) + MATRIX_KEY(2, 0, 0x62) + MATRIX_KEY(2, 1, 0x0c) + MATRIX_KEY(2, 2, 0x1f) + MATRIX_KEY(2, 3, 0x07) + MATRIX_KEY(2, 4, 0x13) + MATRIX_KEY(2, 5, 0x06) + MATRIX_KEY(2, 6, 0x10) + MATRIX_KEY(2, 7, 0x05) + MATRIX_KEY(2, 8, 0x19) + MATRIX_KEY(3, 0, 0x27) + MATRIX_KEY(3, 1, 0x37) + MATRIX_KEY(3, 2, 0x18) + MATRIX_KEY(3, 3, 0x0a) + MATRIX_KEY(3, 4, 0x31) + MATRIX_KEY(3, 5, 0x09) + MATRIX_KEY(3, 6, 0x32) + MATRIX_KEY(3, 7, 0x08) + MATRIX_KEY(3, 8, 0x26) + MATRIX_KEY(4, 0, 0x28) + MATRIX_KEY(4, 1, 0x35) + MATRIX_KEY(4, 2, 0x25) + MATRIX_KEY(4, 4, 0x24) + MATRIX_KEY(4, 6, 0x17) + MATRIX_KEY(4, 8, 0x23) + MATRIX_KEY(5, 0, 0x28) + MATRIX_KEY(5, 2, 0x22) + MATRIX_KEY(5, 3, 0x1b) + MATRIX_KEY(5, 4, 0x21) + MATRIX_KEY(5, 5, 0x1a) + MATRIX_KEY(5, 6, 0x12) + MATRIX_KEY(5, 7, 0x6f) + MATRIX_KEY(5, 8, 0x20) + MATRIX_KEY(5, 9, 0x2a) + MATRIX_KEY(6, 1, 0x1c) + MATRIX_KEY(6, 2, 0x2e) + MATRIX_KEY(6, 3, 0x68) + MATRIX_KEY(6, 4, 0x30) + MATRIX_KEY(6, 5, 0x6d) + MATRIX_KEY(6, 6, 0x1e) + MATRIX_KEY(6, 7, 0x01) + MATRIX_KEY(6, 8, 0x2b) + MATRIX_KEY(6, 9, 0x0f) + MATRIX_KEY(7, 0, 0x67) + MATRIX_KEY(7, 2, 0x6a) + MATRIX_KEY(7, 4, 0x6c) + MATRIX_KEY(7, 6, 0x69) + MATRIX_KEY(7, 7, 0x0e) + MATRIX_KEY(7, 8, 0x1d) + MATRIX_KEY(7, 10, 0x0d) >; }; =20 diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.= dts index 837dbdd9af552..96c48fc522035 100644 --- a/arch/arm/boot/dts/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -6,6 +6,8 @@ */ /dts-v1/; =20 +#include + /include/ "nspire.dtsi" =20 &lcd { @@ -45,28 +47,72 @@ &ahb_clk { =20 &keypad { linux,keymap =3D < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; + MATRIX_KEY(0, 0, 0x1c) + MATRIX_KEY(0, 1, 0x1c) + MATRIX_KEY(0, 4, 0x39) + MATRIX_KEY(0, 5, 0x2c) + MATRIX_KEY(0, 6, 0x15) + MATRIX_KEY(0, 7, 0x0b) + MATRIX_KEY(0, 8, 0x0f) + MATRIX_KEY(1, 0, 0x2d) + MATRIX_KEY(1, 1, 0x11) + MATRIX_KEY(1, 2, 0x2f) + MATRIX_KEY(1, 3, 0x04) + MATRIX_KEY(1, 4, 0x16) + MATRIX_KEY(1, 5, 0x14) + MATRIX_KEY(1, 6, 0x1f) + MATRIX_KEY(1, 7, 0x02) + MATRIX_KEY(1, 10, 0x6a) + MATRIX_KEY(2, 0, 0x13) + MATRIX_KEY(2, 1, 0x10) + MATRIX_KEY(2, 2, 0x19) + MATRIX_KEY(2, 3, 0x07) + MATRIX_KEY(2, 4, 0x18) + MATRIX_KEY(2, 5, 0x31) + MATRIX_KEY(2, 6, 0x32) + MATRIX_KEY(2, 7, 0x05) + MATRIX_KEY(2, 8, 0x28) + MATRIX_KEY(2, 9, 0x6c) + MATRIX_KEY(3, 0, 0x26) + MATRIX_KEY(3, 1, 0x25) + MATRIX_KEY(3, 2, 0x24) + MATRIX_KEY(3, 3, 0x0a) + MATRIX_KEY(3, 4, 0x17) + MATRIX_KEY(3, 5, 0x23) + MATRIX_KEY(3, 6, 0x22) + MATRIX_KEY(3, 7, 0x08) + MATRIX_KEY(3, 8, 0x35) + MATRIX_KEY(3, 9, 0x69) + MATRIX_KEY(4, 0, 0x21) + MATRIX_KEY(4, 1, 0x12) + MATRIX_KEY(4, 2, 0x20) + MATRIX_KEY(4, 4, 0x2e) + MATRIX_KEY(4, 5, 0x30) + MATRIX_KEY(4, 6, 0x1e) + MATRIX_KEY(4, 7, 0x0d) + MATRIX_KEY(4, 8, 0x37) + MATRIX_KEY(4, 9, 0x67) + MATRIX_KEY(5, 1, 0x38) + MATRIX_KEY(5, 2, 0x0c) + MATRIX_KEY(5, 3, 0x1b) + MATRIX_KEY(5, 4, 0x34) + MATRIX_KEY(5, 5, 0x1a) + MATRIX_KEY(5, 6, 0x06) + MATRIX_KEY(5, 8, 0x27) + MATRIX_KEY(5, 9, 0x0e) + MATRIX_KEY(5, 10, 0x6f) + MATRIX_KEY(6, 0, 0x2b) + MATRIX_KEY(6, 2, 0x4e) + MATRIX_KEY(6, 3, 0x68) + MATRIX_KEY(6, 4, 0x03) + MATRIX_KEY(6, 5, 0x6d) + MATRIX_KEY(6, 6, 0x09) + MATRIX_KEY(6, 7, 0x01) + MATRIX_KEY(6, 9, 0x0f) + MATRIX_KEY(7, 8, 0x2a) + MATRIX_KEY(7, 9, 0x1d) + MATRIX_KEY(7, 10, 0x33) + >; }; =20 &vbus_reg { diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.= dts index f7d0faacd4ccd..235cd4264da79 100644 --- a/arch/arm/boot/dts/nspire-tp.dts +++ b/arch/arm/boot/dts/nspire-tp.dts @@ -6,32 +6,78 @@ */ /dts-v1/; =20 +#include + /include/ "nspire-classic.dtsi" =20 &keypad { linux,keymap =3D < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; + MATRIX_KEY(0, 0, 0x1c) + MATRIX_KEY(0, 1, 0x1c) + MATRIX_KEY(0, 4, 0x39) + MATRIX_KEY(0, 5, 0x2c) + MATRIX_KEY(0, 6, 0x15) + MATRIX_KEY(0, 7, 0x0b) + MATRIX_KEY(0, 8, 0x0f) + MATRIX_KEY(1, 0, 0x2d) + MATRIX_KEY(1, 1, 0x11) + MATRIX_KEY(1, 2, 0x2f) + MATRIX_KEY(1, 3, 0x04) + MATRIX_KEY(1, 4, 0x16) + MATRIX_KEY(1, 5, 0x14) + MATRIX_KEY(1, 6, 0x1f) + MATRIX_KEY(1, 7, 0x02) + MATRIX_KEY(1, 10, 0x6a) + MATRIX_KEY(2, 0, 0x13) + MATRIX_KEY(2, 1, 0x10) + MATRIX_KEY(2, 2, 0x19) + MATRIX_KEY(2, 3, 0x07) + MATRIX_KEY(2, 4, 0x18) + MATRIX_KEY(2, 5, 0x31) + MATRIX_KEY(2, 6, 0x32) + MATRIX_KEY(2, 7, 0x05) + MATRIX_KEY(2, 8, 0x28) + MATRIX_KEY(2, 9, 0x6c) + MATRIX_KEY(3, 0, 0x26) + MATRIX_KEY(3, 1, 0x25) + MATRIX_KEY(3, 2, 0x24) + MATRIX_KEY(3, 3, 0x0a) + MATRIX_KEY(3, 4, 0x17) + MATRIX_KEY(3, 5, 0x23) + MATRIX_KEY(3, 6, 0x22) + MATRIX_KEY(3, 7, 0x08) + MATRIX_KEY(3, 8, 0x35) + MATRIX_KEY(3, 9, 0x69) + MATRIX_KEY(4, 0, 0x21) + MATRIX_KEY(4, 1, 0x12) + MATRIX_KEY(4, 2, 0x20) + MATRIX_KEY(4, 4, 0x2e) + MATRIX_KEY(4, 5, 0x30) + MATRIX_KEY(4, 6, 0x1e) + MATRIX_KEY(4, 7, 0x0d) + MATRIX_KEY(4, 8, 0x37) + MATRIX_KEY(4, 9, 0x67) + MATRIX_KEY(5, 1, 0x38) + MATRIX_KEY(5, 2, 0x0c) + MATRIX_KEY(5, 3, 0x1b) + MATRIX_KEY(5, 4, 0x34) + MATRIX_KEY(5, 5, 0x1a) + MATRIX_KEY(5, 6, 0x06) + MATRIX_KEY(5, 8, 0x27) + MATRIX_KEY(5, 9, 0x0e) + MATRIX_KEY(5, 10, 0x6f) + MATRIX_KEY(6, 0, 0x2b) + MATRIX_KEY(6, 2, 0x4e) + MATRIX_KEY(6, 3, 0x68) + MATRIX_KEY(6, 4, 0x03) + MATRIX_KEY(6, 5, 0x6d) + MATRIX_KEY(6, 6, 0x09) + MATRIX_KEY(6, 7, 0x01) + MATRIX_KEY(6, 9, 0x0f) + MATRIX_KEY(7, 8, 0x2a) + MATRIX_KEY(7, 9, 0x1d) + MATRIX_KEY(7, 10, 0x33) + >; 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Tue, 1 Nov 2022 16:58:11 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44t117953; Tue, 1 Nov 2022 16:58:10 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 8/9] ARM: nspire: Use syscon-reboot to handle restart Date: Tue, 1 Nov 2022 16:58:03 -0500 Message-ID: <20221101215804.16262-9-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Writing this bit can be handled by the DT syscon-reboot driver. Enable that driver and remove the machine_desc version. Signed-off-by: Andrew Davis Reviewed-by: Linus Walleij Tested-by: Fabian Vogt Reviewed-by: Fabian Vogt --- arch/arm/mach-nspire/Kconfig | 2 ++ arch/arm/mach-nspire/mmio.h | 3 --- arch/arm/mach-nspire/nspire.c | 10 ---------- 3 files changed, 2 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig index b7a3871876d75..0ffdcaca1e6b4 100644 --- a/arch/arm/mach-nspire/Kconfig +++ b/arch/arm/mach-nspire/Kconfig @@ -9,5 +9,7 @@ config ARCH_NSPIRE select ARM_VIC select ARM_TIMER_SP804 select NSPIRE_TIMER + select POWER_RESET + select POWER_RESET_SYSCON help This enables support for systems using the TI-NSPIRE CPU diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h index 48e32f13f3119..2ce0656139ece 100644 --- a/arch/arm/mach-nspire/mmio.h +++ b/arch/arm/mach-nspire/mmio.h @@ -5,9 +5,6 @@ * Copyright (C) 2013 Daniel Tang */ =20 -#define NSPIRE_MISC_PHYS_BASE 0x900A0000 -#define NSPIRE_MISC_HWRESET 0x08 - #define NSPIRE_PWR_PHYS_BASE 0x900B0000 #define NSPIRE_PWR_VIRT_BASE 0xFEEB0000 #define NSPIRE_PWR_BUS_DISABLE1 0x18 diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c index 2d4abb0288b9d..1e13337972dd5 100644 --- a/arch/arm/mach-nspire/nspire.c +++ b/arch/arm/mach-nspire/nspire.c @@ -27,16 +27,6 @@ static const char *const nspire_dt_match[] __initconst = =3D { NULL, }; =20 -static void nspire_restart(enum reboot_mode mode, const char *cmd) -{ - void __iomem *base =3D ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K); - if (!base) - return; - - writel(2, base + NSPIRE_MISC_HWRESET); -} - DT_MACHINE_START(NSPIRE, "TI-NSPIRE") .dt_compat =3D nspire_dt_match, - .restart =3D nspire_restart, MACHINE_END --=20 2.37.3 From nobody Thu Apr 9 01:42:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 460F3C4332F for ; Tue, 1 Nov 2022 21:59:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231182AbiKAV64 (ORCPT ); Tue, 1 Nov 2022 17:58:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230464AbiKAV6e (ORCPT ); Tue, 1 Nov 2022 17:58:34 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEDD962EA; Tue, 1 Nov 2022 14:58:29 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1LwBX6078821; Tue, 1 Nov 2022 16:58:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667339891; bh=cHnsszYskhB1r83xPBikQhEqNPiLQZB7+eb0qaod38g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NSPuHMsljjTP/bEAocG5+ghIPd5CQLpH+XWopl84/o/1vXlC4s0nz9e3qd1+m6Dde av1ui0ztc2iOypokv1VcoP+Z3penpSSI49FEPkMp6FIFnElCPsvrnsAasVL7o+xAFV aiS/BTGg0ykhKUjOfl/XVd7po9aPFbZ8MbhVg/aQ= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1LwBdh021680 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 16:58:11 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 16:58:11 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 16:58:11 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1Lw44u117953; Tue, 1 Nov 2022 16:58:10 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v4 9/9] ARM: nspire: Remove unused header file mmio.h Date: Tue, 1 Nov 2022 16:58:04 -0500 Message-ID: <20221101215804.16262-10-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101215804.16262-1-afd@ti.com> References: <20221101215804.16262-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Nspire boardfile platform drivers have all been converted. None of the definitions in this header are used anymore. Remove it. While here lets remove all the other unused headers and the file name from in the file itself. Signed-off-by: Andrew Davis --- arch/arm/mach-nspire/mmio.h | 13 ------------- arch/arm/mach-nspire/nspire.c | 14 -------------- 2 files changed, 27 deletions(-) delete mode 100644 arch/arm/mach-nspire/mmio.h diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h deleted file mode 100644 index 2ce0656139ece..0000000000000 --- a/arch/arm/mach-nspire/mmio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/arch/arm/mach-nspire/mmio.h - * - * Copyright (C) 2013 Daniel Tang - */ - -#define NSPIRE_PWR_PHYS_BASE 0x900B0000 -#define NSPIRE_PWR_VIRT_BASE 0xFEEB0000 -#define NSPIRE_PWR_BUS_DISABLE1 0x18 -#define NSPIRE_PWR_BUS_DISABLE2 0x20 - -#define NSPIRE_LCD_PHYS_BASE 0xC0000000 diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c index 1e13337972dd5..2fbfc23237ffe 100644 --- a/arch/arm/mach-nspire/nspire.c +++ b/arch/arm/mach-nspire/nspire.c @@ -1,23 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/mach-nspire/nspire.c - * * Copyright (C) 2013 Daniel Tang */ -#include -#include -#include -#include -#include -#include -#include -#include =20 #include -#include -#include - -#include "mmio.h" =20 static const char *const nspire_dt_match[] __initconst =3D { "ti,nspire", --=20 2.37.3