From nobody Sun Feb 8 08:13:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCFB9C4332F for ; Tue, 1 Nov 2022 18:10:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231173AbiKASKF (ORCPT ); Tue, 1 Nov 2022 14:10:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230261AbiKASJp (ORCPT ); Tue, 1 Nov 2022 14:09:45 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B980A1D0D0; Tue, 1 Nov 2022 11:09:43 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9Z8X066871; Tue, 1 Nov 2022 13:09:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667326175; bh=zuc2d798pjg2cZJq4aTsVQVxPd6NLeA8WTnzeqH9IYg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nml7eN3xtPKWgOOOSL7rto7+nj8u1GpdloyYEmZgo5jcVCW2wH4ediMZETDxTMR1a 2DlKPYUDatjrCDB5T4E8iNG6RE5M00ADQqc6b085ECoVxjFbDj0sVsydSR6nYMPASk q7ysvErDYA7UyaehMIEGeV2kCojNOBv40wEDkA+A= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1I9Zdl076789 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 13:09:35 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 13:09:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 13:09:35 -0500 Received: from maitri.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9ZVm008602; Tue, 1 Nov 2022 13:09:35 -0500 From: Vibhore Vardhan To: , , , , , , CC: , , , Subject: [PATCH RESEND 1/5] cpufreq: ti-cpufreq: Add support for AM625 Date: Tue, 1 Nov 2022 13:09:31 -0500 Message-ID: <20221101180935.139268-2-vibhore@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221101180935.139268-1-vibhore@ti.com> References: <20221101180935.139268-1-vibhore@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dave Gerlach Add support for TI K3 AM625 SoC to read speed and revision values from hardware and pass to OPP layer. Signed-off-by: Dave Gerlach Signed-off-by: Vibhore Vardhan --- drivers/cpufreq/ti-cpufreq.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index f64180dd2005..be4209d97cb3 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -39,6 +39,14 @@ #define OMAP34xx_ProdID_SKUID 0x4830A20C #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270) =20 +#define AM625_EFUSE_K_MPU_OPP 11 +#define AM625_EFUSE_S_MPU_OPP 19 +#define AM625_EFUSE_T_MPU_OPP 20 + +#define AM625_SUPPORT_K_MPU_OPP BIT(0) +#define AM625_SUPPORT_S_MPU_OPP BIT(1) +#define AM625_SUPPORT_T_MPU_OPP BIT(2) + #define VERSION_COUNT 2 =20 struct ti_cpufreq_data; @@ -104,6 +112,25 @@ static unsigned long omap3_efuse_xlate(struct ti_cpufr= eq_data *opp_data, return BIT(efuse); } =20 +static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + unsigned long calculated_efuse =3D AM625_SUPPORT_K_MPU_OPP; + + switch (efuse) { + case AM625_EFUSE_T_MPU_OPP: + calculated_efuse |=3D AM625_SUPPORT_T_MPU_OPP; + fallthrough; + case AM625_EFUSE_S_MPU_OPP: + calculated_efuse |=3D AM625_SUPPORT_S_MPU_OPP; + fallthrough; + case AM625_EFUSE_K_MPU_OPP: + calculated_efuse |=3D AM625_SUPPORT_K_MPU_OPP; + } + + return calculated_efuse; +} + static struct ti_cpufreq_soc_data am3x_soc_data =3D { .efuse_xlate =3D amx3_efuse_xlate, .efuse_fallback =3D AM33XX_800M_ARM_MPU_MAX_FREQ, @@ -198,6 +225,14 @@ static struct ti_cpufreq_soc_data am3517_soc_data =3D { .multi_regulator =3D false, }; =20 +static struct ti_cpufreq_soc_data am625_soc_data =3D { + .efuse_xlate =3D am625_efuse_xlate, + .efuse_offset =3D 0x0018, + .efuse_mask =3D 0x07c0, + .efuse_shift =3D 0x6, + .rev_offset =3D 0x0014, + .multi_regulator =3D false, +}; =20 /** * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC @@ -301,6 +336,7 @@ static const struct of_device_id ti_cpufreq_of_match[] = =3D { { .compatible =3D "ti,dra7", .data =3D &dra7_soc_data }, { .compatible =3D "ti,omap34xx", .data =3D &omap34xx_soc_data, }, { .compatible =3D "ti,omap36xx", .data =3D &omap36xx_soc_data, }, + { .compatible =3D "ti,am625", .data =3D &am625_soc_data, }, /* legacy */ { .compatible =3D "ti,omap3430", .data =3D &omap34xx_soc_data, }, { .compatible =3D "ti,omap3630", .data =3D &omap36xx_soc_data, }, --=20 2.34.1 From nobody Sun Feb 8 08:13:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DD14C4167E for ; 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Tue, 1 Nov 2022 13:09:35 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 13:09:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 13:09:35 -0500 Received: from maitri.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9ZVn008602; Tue, 1 Nov 2022 13:09:35 -0500 From: Vibhore Vardhan To: , , , , , , CC: , , , Subject: [PATCH RESEND 2/5] cpufreq: dt-platdev: Blacklist ti,am625 SoC Date: Tue, 1 Nov 2022 13:09:32 -0500 Message-ID: <20221101180935.139268-3-vibhore@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221101180935.139268-1-vibhore@ti.com> References: <20221101180935.139268-1-vibhore@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dave Gerlach Add ti,am625 SoC to the blacklist as the ti-cpufreq driver will handle creating the cpufreq-dt platform device after it completes so it is not created twice. Signed-off-by: Dave Gerlach Signed-off-by: Vibhore Vardhan --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index 6ac3800db450..85ee11f79840 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -160,6 +160,7 @@ static const struct of_device_id blocklist[] __initcons= t =3D { { .compatible =3D "ti,am43", }, { .compatible =3D "ti,dra7", }, { .compatible =3D "ti,omap3", }, + { .compatible =3D "ti,am625", }, =20 { .compatible =3D "qcom,ipq8064", }, { .compatible =3D "qcom,apq8064", }, --=20 2.34.1 From nobody Sun Feb 8 08:13:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9AA3C4332F for ; Tue, 1 Nov 2022 18:09:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230054AbiKASJy (ORCPT ); Tue, 1 Nov 2022 14:09:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230269AbiKASJp (ORCPT ); Tue, 1 Nov 2022 14:09:45 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C22211D0E4; Tue, 1 Nov 2022 11:09:43 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9ZVJ066875; Tue, 1 Nov 2022 13:09:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667326175; bh=sYCY33KPfAH2okxd/wuioVGmv9vi3bO3eoM0E9eu7Qw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hrC56V3f3JOjBbj3VectN8+wdF7LeGXO91v6A88Kj0UJ/7nFhl1tJmSnwrxwcRpsL HlFIjkuZ3P4YJqJr1ZKfPe+KV2GhkmfqB8XGjaaYhI7k9xuvRxzQvnHCV5T7lGnRxa CUvVDRQG9DgEa2RVJO8hIulUBblnUHNl4uXTZ5NI= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1I9ZjT104244 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 13:09:35 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 13:09:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 13:09:35 -0500 Received: from maitri.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9ZVo008602; Tue, 1 Nov 2022 13:09:35 -0500 From: Vibhore Vardhan To: , , , , , , CC: , , , Subject: [PATCH RESEND 3/5] arm64: dts: ti: k3-am625: Introduce operating-points table Date: Tue, 1 Nov 2022 13:09:33 -0500 Message-ID: <20221101180935.139268-4-vibhore@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221101180935.139268-1-vibhore@ti.com> References: <20221101180935.139268-1-vibhore@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dave Gerlach Introduce an operating-points table for the A53 cores, containing only frequency values as this platform operates on a fixed voltage for the CPUs. Also provide opp-supported-hw values to ensure appropriate OPPs are enabled based on which type of silicon is in use. The latency between pre and post frequency transition was measured in CPUFreq driver for all combinations of OPP changes. The average value was selected as overall clock-latency-ns. Signed-off-by: Dave Gerlach Signed-off-by: Vibhore Vardhan --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/= k3-am625.dtsi index 887f31c23fef..cea2cc7de5dd 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -48,6 +48,8 @@ cpu0: cpu@0 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&L2_0>; + operating-points-v2 =3D <&a53_opp_table>; + clocks =3D <&k3_clks 135 0>; }; =20 cpu1: cpu@1 { @@ -62,6 +64,8 @@ cpu1: cpu@1 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&L2_0>; + operating-points-v2 =3D <&a53_opp_table>; + clocks =3D <&k3_clks 136 0>; }; =20 cpu2: cpu@2 { @@ -76,6 +80,8 @@ cpu2: cpu@2 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&L2_0>; + operating-points-v2 =3D <&a53_opp_table>; + clocks =3D <&k3_clks 137 0>; }; =20 cpu3: cpu@3 { @@ -90,6 +96,51 @@ cpu3: cpu@3 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&L2_0>; + operating-points-v2 =3D <&a53_opp_table>; + clocks =3D <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible =3D "operating-points-v2-ti-cpu"; + opp-shared; + syscon =3D <&wkup_conf>; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-supported-hw =3D <0x01 0x0006>; + clock-latency-ns =3D <6000000>; + }; + + opp-1250000000 { + opp-hz =3D /bits/ 64 <1250000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + opp-suspend; }; }; =20 --=20 2.34.1 From nobody Sun Feb 8 08:13:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6850FC4332F for ; Tue, 1 Nov 2022 18:09:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231177AbiKASJ6 (ORCPT ); Tue, 1 Nov 2022 14:09:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbiKASJp (ORCPT ); Tue, 1 Nov 2022 14:09:45 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 978FB1CFD1; Tue, 1 Nov 2022 11:09:44 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9ZrA080819; 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Tue, 1 Nov 2022 13:09:35 -0500 Received: from maitri.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9ZVp008602; Tue, 1 Nov 2022 13:09:35 -0500 From: Vibhore Vardhan To: , , , , , , CC: , , , Subject: [PATCH RESEND 4/5] cpufreq: ti: Enable ti-cpufreq for ARCH_K3 Date: Tue, 1 Nov 2022 13:09:34 -0500 Message-ID: <20221101180935.139268-5-vibhore@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221101180935.139268-1-vibhore@ti.com> References: <20221101180935.139268-1-vibhore@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dave Gerlach Make ti-cpufreq driver depend on ARCH_K3 and set it to `default y` so it is always enabled for platforms that it depends on. Signed-off-by: Dave Gerlach Signed-off-by: Vibhore Vardhan --- drivers/cpufreq/Kconfig.arm | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 82e5de1f6f8c..be590f498e6a 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -340,8 +340,8 @@ config ARM_TEGRA194_CPUFREQ =20 config ARM_TI_CPUFREQ bool "Texas Instruments CPUFreq support" - depends on ARCH_OMAP2PLUS - default ARCH_OMAP2PLUS + depends on ARCH_OMAP2PLUS || ARCH_K3 + default y help This driver enables valid OPPs on the running platform based on values contained within the SoC in use. Enable this in order to --=20 2.34.1 From nobody Sun Feb 8 08:13:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63CE5C4332F for ; Tue, 1 Nov 2022 18:10:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231181AbiKASKB (ORCPT ); Tue, 1 Nov 2022 14:10:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230425AbiKASJp (ORCPT ); Tue, 1 Nov 2022 14:09:45 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF14B1D0E8; Tue, 1 Nov 2022 11:09:44 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9aTH083738; Tue, 1 Nov 2022 13:09:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667326176; bh=aHfPf+ay0vTuzra6DofDgrduM8g8o28Yub+/Uu/B19Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JEcSkaHC0ykuoH7zYS+XXHizmjO16pr52Iia2v2KstNUeKlbq4Dlaoa2t0/rUEdDE LaQ0QaThHIzm5m7CkqX0Bjeoruuh3m9+oayawUri/itWVr7KVegvHOTn52BsSVfl3Q 2JljI14U7FQI6qUSiYEiocfHYiH5eGQLXLtmN+ls= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A1I9alH017625 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Nov 2022 13:09:36 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 1 Nov 2022 13:09:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 1 Nov 2022 13:09:35 -0500 Received: from maitri.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A1I9ZVq008602; Tue, 1 Nov 2022 13:09:35 -0500 From: Vibhore Vardhan To: , , , , , , CC: , , , Subject: [PATCH RESEND 5/5] arm64: dts: ti: k3-am625-sk: Add 1.4GHz OPP Date: Tue, 1 Nov 2022 13:09:35 -0500 Message-ID: <20221101180935.139268-6-vibhore@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221101180935.139268-1-vibhore@ti.com> References: <20221101180935.139268-1-vibhore@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 1.4 GHz OPP requires supported silicon variant (T speed grade) and also VDD_CORE to be at 0.85V. All production revisions of the AM625-SK have both so we can enable the 1.4 GHz OPP for it. Any other boards based on this design should verify that they have the right silicon variant and the right power tree before adding 1.4 GHz support in their board dts file. Signed-off-by: Vibhore Vardhan --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/t= i/k3-am625-sk.dts index 93a5f0817efc..4620ef5e19bb 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -31,6 +31,15 @@ chosen { bootargs =3D "console=3DttyS2,115200n8 earlycon=3Dns16550a,mmio32,0x0280= 0000"; }; =20 + opp-table { + /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + }; + }; + memory@80000000 { device_type =3D "memory"; /* 2G RAM */ --=20 2.34.1