From nobody Thu Apr 9 03:28:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 140E4C433FE for ; Tue, 1 Nov 2022 14:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230363AbiKAOfP (ORCPT ); Tue, 1 Nov 2022 10:35:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230083AbiKAOez (ORCPT ); Tue, 1 Nov 2022 10:34:55 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4C3F1C118 for ; Tue, 1 Nov 2022 07:34:53 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id p15-20020a17090a348f00b002141615576dso1298558pjb.4 for ; Tue, 01 Nov 2022 07:34:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9ifdhfU8MRp8KF9HZ6tJ7EpItneJOYFyI/sq447ebfo=; b=iXsZ75ohvlLpVxjFccfmFbBkL6VbVZfEchOACqA6t6MtqpmZmZO1++5Rxd6JaFaH8Z U8IT5NK0BgAMRMXNcOHilOESGz40w1nGDhid5y2SOZYSn6pEP5+mcrpoeb1MVkBl7ovz SYAID8JZo1/EcdKB7NolWqkZJBEwVIcfQLPaT/kpMHgCqAG/mjbg7n9pu3xJA4qdUhrO et8uco67UUyAZUzUOg8R/4CRE1OzhjX3wWijU+xmDP1fHMLbSXkkLMG14Eu34Avmhu9r grKTmKiydkgYZUfSO2K0ZhdLgVHpgBNWYRbG7Clqsok20cPjlG236HbAt3jZ60M1VxsF N1QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9ifdhfU8MRp8KF9HZ6tJ7EpItneJOYFyI/sq447ebfo=; b=qltVIR/MzaIsT8hJ9DMLrfc3gY2mYG7gUVOQCIUhP+ikB+KSbM7zVIoTKuknARHCA9 eOZZYmgAj+NhNwd2II91z6oJvxdeC/RzyeeztPZVr/DzpGSK1VgRi1N4kXSQBQvZ1rm8 xyFLIx6AhiikNSNyygpcw0IdwCA6rb4WJCwfYWx/znLu57HOQJ4DgPoiqqqUZtDXzSPf V4amsnPw1fdysd/g7ixG/spbapMJAWYd9VPGgnLYCx50yKPEUvRA11MFoIFdZC14b/1M F9qzj593TIvf8+MopkTqqkXW4hMqEXdMvlIwn5FoK6k2yR7Rto6YrvvSq7sFaz5/IjvS iZrQ== X-Gm-Message-State: ACrzQf3FDHxtbzHKeaolxxDUOgYWNW0y8C2mv9IsKq/cEe0PJkq9+uFw K9bOAVpl/wFXpuwMPVx8A3I6Sg== X-Google-Smtp-Source: AMsMyM5icH7ull/dULpkY3zHwi0hXaybR/0L7dhwshSqo564b6/XpLLLhqwmx1k7xc0i/yPuxhpD+Q== X-Received: by 2002:a17:902:ea09:b0:187:3274:2460 with SMTP id s9-20020a170902ea0900b0018732742460mr5680497plg.153.1667313293078; Tue, 01 Nov 2022 07:34:53 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.52]) by smtp.gmail.com with ESMTPSA id o20-20020a170903009400b0018685aaf41dsm6449055pld.18.2022.11.01.07.34.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 07:34:52 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v10 5/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs Date: Tue, 1 Nov 2022 20:03:58 +0530 Message-Id: <20221101143400.690000-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221101143400.690000-1-apatel@ventanamicro.com> References: <20221101143400.690000-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the supervisor mode (i.e. RISC-V kernel) instead of using SBI calls. The upcoming AIA IMSIC devices allow direct IPI injection from the supervisor mode (i.e. RISC-V kernel). To support this, we extend the riscv_ipi_set_virq_range() function so that IPI provider (i.e. irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/sbi-ipi.c | 2 +- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 79ed0b73cd4e..56976e41a21e 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; =20 #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); =20 /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr); +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) =20 /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -93,10 +101,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } =20 -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } =20 +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ =20 #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c index f0a78420b127..ee8620104bd8 100644 --- a/arch/riscv/kernel/sbi-ipi.c +++ b/arch/riscv/kernel/sbi-ipi.c @@ -75,6 +75,6 @@ void __init sbi_ipi_init(void) "irqchip/sbi-ipi:starting", sbi_ipi_starting_cpu, sbi_ipi_dying_cpu); =20 - riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, false); pr_info("providing IPIs using SBI IPI extension\n"); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index e8a20454d65b..74b8cb1a89ab 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -145,7 +145,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } =20 -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; =20 @@ -168,6 +171,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) =20 /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); =20 diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index f9dd746a72c5..658049a5440b 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -249,7 +249,7 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) goto fail_free_irq; } =20 - riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, true); clint_clear_ipi(clint_ipi_irq, NULL); =20 return 0; --=20 2.34.1