From nobody Sat Sep 21 11:54:20 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66822FA373D for ; Tue, 1 Nov 2022 06:11:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229940AbiKAGL4 (ORCPT ); Tue, 1 Nov 2022 02:11:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229891AbiKAGLr (ORCPT ); Tue, 1 Nov 2022 02:11:47 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A23910FD6; Mon, 31 Oct 2022 23:11:45 -0700 (PDT) X-UUID: 160aec99e83f4ba3bf889cedd7bfe111-20221101 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=kA5JNRTKDV1dAItHbDmK5oovg/tPz2PC0c+hpfEzm2c=; b=sCWJbizksz+qi5+bJn5rAGUPje8tRQ9RHy4Cytoaqy3AccI7HU02K8QBYYRp3UgxBmlyNR+fyXdzNnOXloSM3wPqMQAczE4hnGy9++i1l0wwc5ePChFDLF12/5F3/ApTwaRjKC7NkbAB6RDhbtVI1PMOyuYnUWARxjEpZaJbkIk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:ea80708a-db00-4f5f-95c5-95b8b37a27b6,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.12,REQID:ea80708a-db00-4f5f-95c5-95b8b37a27b6,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:62cd327,CLOUDID:77433590-1a78-4832-bd08-74b1519dcfbf,B ulkID:221101141142JXVKS36F,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 160aec99e83f4ba3bf889cedd7bfe111-20221101 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2019377883; Tue, 01 Nov 2022 14:11:40 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 1 Nov 2022 14:11:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 1 Nov 2022 14:11:39 +0800 From: Tinghan Shen To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Pierre-Louis Bossart , Liam Girdwood , Peter Ujfalusi , Bard Liao , Ranjani Sridharan , Kai Vehmanen , Daniel Baluta , Mark Brown , Jaroslav Kysela , Takashi Iwai , Tinghan Shen , Yaochun Hung CC: , , , , , , Subject: [PATCH v1 1/2] dt-bindings: dsp: mediatek: Add default clock sources for mt8186 dsp Date: Tue, 1 Nov 2022 14:11:36 +0800 Message-ID: <20221101061137.25731-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221101061137.25731-1-tinghan.shen@mediatek.com> References: <20221101061137.25731-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the default clock sources used by mt8186 dsp. Signed-off-by: Tinghan Shen --- .../devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml= b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml index 3e63f79890b4..4cc0634c876b 100644 --- a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml @@ -35,11 +35,15 @@ properties: items: - description: mux for audio dsp clock - description: mux for audio dsp local bus + - description: default clock source for dsp local bus + - description: default clock source for dsp core =20 clock-names: items: - const: audiodsp - const: adsp_bus + - const: mainpll_d2_d2 + - const: clk26m =20 power-domains: maxItems: 1 @@ -82,9 +86,11 @@ examples: <0x1068f000 0x1000>; reg-names =3D "cfg", "sram", "sec", "bus"; clocks =3D <&topckgen CLK_TOP_AUDIODSP>, - <&topckgen CLK_TOP_ADSP_BUS>; - clock-names =3D "audiodsp", - "adsp_bus"; + <&topckgen CLK_TOP_ADSP_BUS>, + <&topckgen CLK_TOP_MAINPLL_D2_D2>, + <&clk26m>; + clock-names =3D "audiodsp", "adsp_bus", + "mainpll_d2_d2", "clk26m"; power-domains =3D <&spm 6>; mbox-names =3D "rx", "tx"; mboxes =3D <&adsp_mailbox0>, <&adsp_mailbox1>; --=20 2.18.0