From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EF9CECAAA1 for ; Mon, 31 Oct 2022 18:02:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229958AbiJaSCx (ORCPT ); Mon, 31 Oct 2022 14:02:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229845AbiJaSCt (ORCPT ); Mon, 31 Oct 2022 14:02:49 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BF3313D75 for ; Mon, 31 Oct 2022 11:02:44 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id f9so11367586pgj.2 for ; Mon, 31 Oct 2022 11:02:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0IUK7dOZ9Lcdl6uBX0seGC6eqiOVvfBfRi7yzXg7EXo=; b=bQ+V92GVTFKFxiD7r7e5JULUOzF3cPf1Tm2vHCiJCeNSNekLmABdNzuJSfJeiRj2g/ LOSt+9L6uRnlEcr6lU/WBy1Bk2BHC2QDREPgUTUFM/QmdNwOhF21dDWWwZgRuTgKLtFu kNUjwAEYKx3jXvIznyXR/EIbUECkTaX6OhrIREa7SJ+ipLh+a9mSiSz4baKmwmc5j1WE bOUl+9Uc+25djjidXVgmHLCsWMi0dZKZzTEJF47tycWeHM+TH/JRL8jWEeruiHHwoyhs AZm/+gz1Nj72oHO5iYPCru+ZsyiRjrW20NLp/JxomU2TEOsYbtUE/r0J/60CjRupryXg KtjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0IUK7dOZ9Lcdl6uBX0seGC6eqiOVvfBfRi7yzXg7EXo=; b=PPQ50HI+KeRcwqkdZGPpigR4Cr+IoRibtbEXz+nJ5kynAh8unc/qau9hzgrVL91AAI cyb7bh9Fi77OZBryuMAEb9t5iFsWyVeokdv1VMnVCw2Luw5ONqqVpJzlGTuDUwNXatjI zFgZ4h5L+4PeSWbtfRSor6Rk1rtK4yRHtbS9FjxJA7VwrFRgULbAmDXelxDAB9gQZQnF q8ogq9Mou71IETFUXu97nVTLhdQZH8G8Tj7SvLoSr0kspnrt79lmgi+st9T4IK6RZRIJ fPZggPPW8UXuMlKnBcGtgYJu4310+0ivNxGPJC9hhCxn55KqgifqSsMl4ATn0GHb1YWr ARwQ== X-Gm-Message-State: ACrzQf0D9CfxVwat4Q1M/Ra911v1noPX357gxV6NfmxdnrD3So+snPue SJP4a/euw6rVAIHQkMRttFBp X-Google-Smtp-Source: AMsMyM7Oahtyd0+EKqV+9d/FgN2rFhA8nC0AZWemu0AFmC96NsoVMVZcE34BmOdqj/qCKDgtYwj0Ow== X-Received: by 2002:a05:6a00:27a1:b0:566:8937:27c2 with SMTP id bd33-20020a056a0027a100b00566893727c2mr15635363pfb.24.1667239363605; Mon, 31 Oct 2022 11:02:43 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:02:42 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 01/15] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tables struct Date: Mon, 31 Oct 2022 23:32:03 +0530 Message-Id: <20221031180217.32512-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tables struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tables. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 223 +++++++++++++----------- 1 file changed, 126 insertions(+), 97 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index c08d34ad1313..cdfda4e6d575 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -107,7 +107,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPH= Y_LAYOUT_SIZE] =3D { [QPHY_SW_RESET] =3D QPHY_V4_PCS_UFS_SW_RESET, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -156,12 +156,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -175,7 +175,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl= [] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -231,12 +231,12 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), @@ -254,7 +254,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f), @@ -266,7 +266,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), @@ -308,13 +308,13 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -333,7 +333,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -344,7 +344,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -374,7 +374,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -383,7 +383,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -421,7 +421,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_t= bl[] =3D { =20 }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -431,7 +431,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -461,7 +461,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -473,7 +473,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -513,7 +513,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -531,19 +531,24 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pc= s_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +struct qmp_phy_cfg_tables { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes; + int serdes_num; + const struct qmp_phy_init_tbl *tx; + int tx_num; + const struct qmp_phy_init_tbl *rx; + int rx_num; + const struct qmp_phy_init_tbl *pcs; + int pcs_num; +}; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { int lanes; =20 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_cfg_tables tables; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -660,12 +665,14 @@ static const char * const qmp_phy_vreg_l[] =3D { static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes_tbl), - .tx_tbl =3D msm8996_ufs_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx_tbl), - .rx_tbl =3D msm8996_ufs_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx_tbl), + .tables =3D { + .serdes =3D msm8996_ufs_serdes, + .serdes_num =3D ARRAY_SIZE(msm8996_ufs_serdes), + .tx =3D msm8996_ufs_tx, + .tx_num =3D ARRAY_SIZE(msm8996_ufs_tx), + .rx =3D msm8996_ufs_rx, + .rx_num =3D ARRAY_SIZE(msm8996_ufs_rx), + }, =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -685,14 +692,16 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), - .tx_tbl =3D sdm845_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx_tbl), - .rx_tbl =3D sdm845_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx_tbl), - .pcs_tbl =3D sdm845_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), + .tables =3D { + .serdes =3D sdm845_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx =3D sdm845_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx =3D sdm845_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs =3D sdm845_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -709,14 +718,16 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), - .tx_tbl =3D sm6115_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx_tbl), - .rx_tbl =3D sm6115_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx_tbl), - .pcs_tbl =3D sm6115_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), + .tables =3D { + .serdes =3D sm6115_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx =3D sm6115_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx =3D sm6115_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs =3D sm6115_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -732,14 +743,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), - .tx_tbl =3D sm8150_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx_tbl), - .rx_tbl =3D sm8150_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx_tbl), - .pcs_tbl =3D sm8150_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), + .tables =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -754,14 +767,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .tables =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -776,14 +791,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .tables =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -826,16 +843,43 @@ static void qmp_ufs_configure(void __iomem *base, qmp_ufs_configure_lane(base, regs, tbl, num, 0xff); } =20 -static int qmp_ufs_serdes_init(struct qmp_phy *qphy) +static void qmp_ufs_serdes_init(struct qmp_phy *qphy, const struct qmp_phy= _cfg_tables *tables) { const struct qmp_phy_cfg *cfg =3D qphy->cfg; void __iomem *serdes =3D qphy->serdes; - const struct qmp_phy_init_tbl *serdes_tbl =3D cfg->serdes_tbl; - int serdes_tbl_num =3D cfg->serdes_tbl_num; =20 - qmp_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + if (!tables) + return; =20 - return 0; + qmp_ufs_configure(serdes, cfg->regs, tables->serdes, tables->serdes_num); +} + +static void qmp_ufs_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_= cfg_tables *tables) +{ + const struct qmp_phy_cfg *cfg =3D qphy->cfg; + void __iomem *tx =3D qphy->tx; + void __iomem *rx =3D qphy->rx; + + qmp_ufs_configure_lane(tx, cfg->regs, tables->tx, tables->tx_num, 1); + + if (cfg->lanes >=3D 2) + qmp_ufs_configure_lane(qphy->tx2, cfg->regs, tables->tx, tables->tx_num,= 2); + + qmp_ufs_configure_lane(rx, cfg->regs, tables->rx, tables->rx_num, 1); + + if (cfg->lanes >=3D 2) + qmp_ufs_configure_lane(qphy->rx2, cfg->regs, tables->rx, tables->rx_num,= 2); +} + +static void qmp_ufs_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cf= g_tables *tables) +{ + const struct qmp_phy_cfg *cfg =3D qphy->cfg; + void __iomem *pcs =3D qphy->pcs; + + if (!tables) + return; + + qmp_ufs_configure(pcs, cfg->regs, tables->pcs, tables->pcs_num); } =20 static int qmp_ufs_com_init(struct qmp_phy *qphy) @@ -933,31 +977,16 @@ static int qmp_ufs_power_on(struct phy *phy) struct qmp_phy *qphy =3D phy_get_drvdata(phy); struct qcom_qmp *qmp =3D qphy->qmp; const struct qmp_phy_cfg *cfg =3D qphy->cfg; - void __iomem *tx =3D qphy->tx; - void __iomem *rx =3D qphy->rx; void __iomem *pcs =3D qphy->pcs; void __iomem *status; unsigned int mask, val, ready; int ret; =20 - qmp_ufs_serdes_init(qphy); - - /* Tx, Rx, and PCS configurations */ - qmp_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_ufs_serdes_init(qphy, &cfg->tables); =20 - if (cfg->lanes >=3D 2) { - qmp_ufs_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); - } - - qmp_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - - if (cfg->lanes >=3D 2) { - qmp_ufs_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); - } + qmp_ufs_lanes_init(qphy, &cfg->tables); =20 - qmp_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_ufs_pcs_init(qphy, &cfg->tables); =20 ret =3D reset_control_deassert(qmp->ufs_reset); if (ret) --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: 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quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 02/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Date: Mon, 31 Oct 2022 23:32:04 +0530 Message-Id: <20221031180217.32512-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index cdfda4e6d575..4c6a2b5afc9a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -20,6 +20,8 @@ #include #include =20 +#include + #include =20 #include "phy-qcom-qmp.h" @@ -549,6 +551,8 @@ struct qmp_phy_cfg { =20 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_cfg_tables tables; + /* Additional sequence for HS Series B */ + const struct qmp_phy_cfg_tables tables_hs_b; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -582,6 +586,7 @@ struct qmp_phy_cfg { * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc * @qmp: QMP phy to which this lane belongs + * @mode: PHY mode configured by the UFS driver */ struct qmp_phy { struct phy *phy; @@ -594,6 +599,7 @@ struct qmp_phy { void __iomem *rx2; void __iomem *pcs_misc; struct qcom_qmp *qmp; + u32 mode; }; =20 /** @@ -983,6 +989,8 @@ static int qmp_ufs_power_on(struct phy *phy) int ret; =20 qmp_ufs_serdes_init(qphy, &cfg->tables); + if (qphy->mode =3D=3D PHY_MODE_UFS_HS_B) + qmp_ufs_serdes_init(qphy, &cfg->tables_hs_b); =20 qmp_ufs_lanes_init(qphy, &cfg->tables); =20 @@ -1070,6 +1078,15 @@ static int qmp_ufs_disable(struct phy *phy) return qmp_ufs_exit(phy); } =20 +static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submo= de) +{ + struct qmp_phy *qphy =3D phy_get_drvdata(phy); + + qphy->mode =3D mode; + + return 0; +} + static int qmp_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg = *cfg) { struct qcom_qmp *qmp =3D dev_get_drvdata(dev); @@ -1105,6 +1122,7 @@ static int qmp_ufs_clk_init(struct device *dev, const= struct qmp_phy_cfg *cfg) static const struct phy_ops qcom_qmp_ufs_ops =3D { .power_on =3D qmp_ufs_enable, .power_off =3D qmp_ufs_disable, + .set_mode =3D qmp_ufs_set_mode, .owner =3D THIS_MODULE, }; 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Mon, 31 Oct 2022 11:02:57 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.02.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:02:55 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 03/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Date: Mon, 31 Oct 2022 23:32:05 +0530 Message-Id: <20221031180217.32512-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 4c6a2b5afc9a..5f2a012707b7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -553,6 +553,8 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tables tables; /* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tables tables_hs_b; + /* Additional sequence for HS G4 */ + const struct qmp_phy_cfg_tables tables_hs_g4; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -587,6 +589,7 @@ struct qmp_phy_cfg { * @pcs_misc: iomapped memory space for lane's pcs_misc * @qmp: QMP phy to which this lane belongs * @mode: PHY mode configured by the UFS driver + * @submode: PHY submode configured by the UFS driver */ struct qmp_phy { struct phy *phy; @@ -600,6 +603,7 @@ struct qmp_phy { void __iomem *pcs_misc; struct qcom_qmp *qmp; u32 mode; + u32 submode; }; =20 /** @@ -993,8 +997,12 @@ static int qmp_ufs_power_on(struct phy *phy) qmp_ufs_serdes_init(qphy, &cfg->tables_hs_b); =20 qmp_ufs_lanes_init(qphy, &cfg->tables); + if (qphy->submode =3D=3D UFS_HS_G4) + qmp_ufs_lanes_init(qphy, &cfg->tables_hs_g4); =20 qmp_ufs_pcs_init(qphy, &cfg->tables); + if (qphy->submode =3D=3D UFS_HS_G4) + qmp_ufs_pcs_init(qphy, &cfg->tables_hs_g4); =20 ret =3D reset_control_deassert(qmp->ufs_reset); if (ret) @@ -1083,6 +1091,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy= _mode mode, int submode) struct qmp_phy *qphy =3D phy_get_drvdata(phy); =20 qphy->mode =3D mode; + qphy->submode =3D submode; =20 return 0; } --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 003CBFA3746 for ; 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Mon, 31 Oct 2022 11:03:07 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.02.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:03:04 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 04/15] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Date: Mon, 31 Oct 2022 23:32:06 +0530 Message-Id: <20221031180217.32512-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of SM8150. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 68 ++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 5f2a012707b7..fa7457c0202b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -385,6 +385,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), @@ -420,7 +424,32 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), +}; =20 +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), }; =20 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { @@ -433,6 +462,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -774,6 +808,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .phy_status =3D PHYSTATUS, }; =20 +static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D { + .lanes =3D 2, + + .tables =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tables_hs_g4 =3D { + .tx =3D sm8250_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx =3D sm8250_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), + .pcs =3D sm8250_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_pcs), + }, + .clk_list =3D sdm845_ufs_phy_clk_l, + .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8150_ufsphy_regs_layout, + + .start_ctrl =3D SERDES_START, + .pwrdn_ctrl =3D SW_PWRDN, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 @@ -1226,7 +1292,7 @@ static const struct of_device_id qmp_ufs_of_match_tab= le[] =3D { .data =3D &sm8150_ufsphy_cfg, }, { .compatible =3D "qcom,sm8250-qmp-ufs-phy", - .data =3D &sm8150_ufsphy_cfg, + .data =3D &sm8250_ufsphy_cfg, }, { .compatible =3D "qcom,sm8350-qmp-ufs-phy", .data =3D &sm8350_ufsphy_cfg, --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EF4BECAAA1 for ; Mon, 31 Oct 2022 18:03:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230111AbiJaSDi (ORCPT ); Mon, 31 Oct 2022 14:03:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229991AbiJaSDV (ORCPT ); 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Mon, 31 Oct 2022 11:03:13 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 05/15] phy: qcom-qmp-ufs: Move HS Rate B register setting to tables_hs_b Date: Mon, 31 Oct 2022 23:32:07 +0530 Message-Id: <20221031180217.32512-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tables_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 32 +++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index fa7457c0202b..c55c85a8f95e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -228,8 +228,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -305,8 +306,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -371,8 +373,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -492,8 +495,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -746,6 +750,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .pcs =3D sdm845_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), }, + .tables_hs_b =3D { + .serdes =3D sdm845_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -772,6 +780,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .pcs =3D sm6115_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), }, + .tables_hs_b =3D { + .serdes =3D sm6115_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -797,6 +809,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .pcs =3D sm8150_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), }, + .tables_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -829,6 +845,10 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D { .pcs =3D sm8250_ufsphy_hs_g4_pcs, .pcs_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_pcs), }, + .tables_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -853,6 +873,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tables_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A1D4FA3747 for ; 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Mon, 31 Oct 2022 11:03:19 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 06/15] dt-bindings: ufs: Add "max-device-gear" property for UFS device Date: Mon, 31 Oct 2022 23:32:08 +0530 Message-Id: <20221031180217.32512-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The maximum gear supported by the UFS device can be specified using the "max-device-gear" property. This allows the UFS controller to configure the TX/RX gear before starting communication with the UFS device. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/ufs/ufs-common.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Docume= ntation/devicetree/bindings/ufs/ufs-common.yaml index 47a4e9e1a775..5dcd14909ad5 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml @@ -73,6 +73,11 @@ properties: description: Specifies max. load that can be drawn from VCCQ2 supply. =20 + max-device-gear: + description: + Specifies max. gear the UFS device supports. + enum: [1, 2, 3, 4, 5] + dependencies: freq-table-hz: [ 'clocks' ] =20 --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B08EAFA3741 for ; Mon, 31 Oct 2022 18:04:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229980AbiJaSEP (ORCPT ); Mon, 31 Oct 2022 14:04:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230231AbiJaSDd (ORCPT ); Mon, 31 Oct 2022 14:03:33 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAE8013DCC for ; Mon, 31 Oct 2022 11:03:30 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id f140so11366301pfa.1 for ; Mon, 31 Oct 2022 11:03:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=57hrdpD9V7ZTE8+VIgUybXatzD5HV6GvuzYxuyw9ASk=; b=CJZOurchjGJl1snA1fXRSkkVYNfUPtkHRC6arQrhiLHCCHw1eBR+6Q5F0PorDK01ZP 1Hkzf0fYrm4AGRLhb/l3wfkKVNBgGXpBZz3z3lyNlxt/UHoaR6ON+NVV0OQdlT6f2Yy8 rPxHeFts4yxmH20dB/LYHEkv1J/BWTk2zsRd48gC341JSYFCkiRixJFJ2HTJAnrC6piJ NPg8p6A4d8au8odxHziT895HmhU9L+Oc7GlDTzKYcfTZvdYNg7aAhVRnT/7xzXgXRSdl bJY309odjX5XDPSjAt9ir+3anWIHWjKCv5HA/FrmD9Eq5om/RL2latgKPQmGNzOxOzR+ a7wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=57hrdpD9V7ZTE8+VIgUybXatzD5HV6GvuzYxuyw9ASk=; b=ewDIgvPYVrjo6/Lw5OdLM/P+37JNauLmLzabhjgF6FzhWFiBOAk9olIxSApZWmgOhp 02bYLpksP/1uZdW1SNxperHPT6JlrLFM8VfMQ9DaZF4FBvXYlDL2ST6AJ7E5P8w5kcXN vteaIARWZYnAjpIgi0UofhABy6ZWvo43l/bX7A2ZEs/SvAlTqy2cUEWGkKpBuSxvn+w/ jWtJ0i1XPLrl+am3No825RYGFOHCvoTpmk5A5Hk6ssS0sv3Zs4Ulif4DQ6eEk7WKB14+ 4QBAC9lcA0TidgVDt+zJe2MZabfo2HM2DCvB2y+Bn2Sh/PylLcNW2xNkcVfyhJByv+ng aaog== X-Gm-Message-State: ACrzQf2r542X2fXqc0JEOdeRRZ8L33AcYOSj+DzuFHrPco0A2qz2etPp HD9hf9AtfKuLa+g9DH+FhRkN X-Google-Smtp-Source: AMsMyM4YfrwoNrdGfiVoZCqIhrLJ40dbpww+YBMczlctY4waFMDpfmVg0qxipxfjexfRmTW2yYHGGQ== X-Received: by 2002:a63:2d05:0:b0:460:55e3:df91 with SMTP id t5-20020a632d05000000b0046055e3df91mr13774942pgt.177.1667239410304; Mon, 31 Oct 2022 11:03:30 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.03.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:03:29 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 07/15] arm64: dts: qcom: qrb5165-rb5: Add max-device-gear property to UFS node Date: Mon, 31 Oct 2022 23:32:09 +0530 Message-Id: <20221031180217.32512-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add "max-device-gear" property to UFS node to specify the maximum gear speed supported by the UFS device on the RB5 board. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts= /qcom/qrb5165-rb5.dts index bf8077a1cf9a..3cb1f48c90f5 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1250,6 +1250,7 @@ &uart12 { &ufs_mem_hc { status =3D "okay"; =20 + max-device-gear =3D <4>; vcc-supply =3D <&vreg_l17a_3p0>; vcc-max-microamp =3D <800000>; vccq-supply =3D <&vreg_l6a_1p2>; --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 415B2FA3748 for ; Mon, 31 Oct 2022 18:04:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230174AbiJaSEW (ORCPT ); Mon, 31 Oct 2022 14:04:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229487AbiJaSDt (ORCPT ); Mon, 31 Oct 2022 14:03:49 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 788E213E09 for ; Mon, 31 Oct 2022 11:03:37 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d24so11443686pls.4 for ; Mon, 31 Oct 2022 11:03:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SEImNrrGJCLJR7lpSd2nSHN0zzQY9fzqQ71zihD+hPY=; b=qFdedGLrwxmNMAehEwYxGQ6gohQFci3keB8yiTqBT8Aqxw6Uk4ITPICooavU872d4G 2En1DjQOIXxpKU8TDmEYKaAxRG+i7ZmFxNKmaRZOYSkLGgxanLXXcBFNEc6InNFIxaHW 2IAWOTNKH8LuS9xL8lDymF1EwJn31EHRzsbCjLo8F37RhG8UHgG/t9PpTh7+4gyp7OTF E59JFlTkACuPadWq1PK1A9kgkSG0TUKv4FNKqvpJHv3n5vw9pX33Aq0hIol8ekprLwvD 18ROj3kz0ynryLQWXMSdVPxs4OTQPMqLt1zaa5DWjQ7ykOb1+SXaO+8zMrstvpgf50/o 5GfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SEImNrrGJCLJR7lpSd2nSHN0zzQY9fzqQ71zihD+hPY=; b=nwHc+HMqvubiF30xm9DIwv10AYl4lpbBdDW6DP8JOajkVxhPKMFBHPZ1Sgkle43iBp Hs2FhvWi2BwzQDBEW9KrWivKMnNNma3nxsK5H5SHXzQ7FRSIFh0myri++UmQfq1ABTqi Ztdqs64Znl5XL5jtw7HptG2DPWNOLvoDyGowv4YFSY32SGYpEX0EJQ/YXgh4v5hEL9wG sn+Kk4qMOM6qdDQZmhr/OMsj/PQO0It2DcW5apMB+LqZTnkIMQ6KLUAzUJznsRVm09nD UguvRjCqyH3Rep6i86CkbDJVK0Ri0tE83iV7nh5QzGw3P2TqwJHD0WfhMF/9NcgVWcHd AJJw== X-Gm-Message-State: ACrzQf1K3vapd1hpmS9a4EIMEH8CzVwl04gsZsiZcDz/jgmD2oy6cLvG fp5qDK5P2p+IGecmb73s3dd2 X-Google-Smtp-Source: AMsMyM712xgW8kAEoVLy0cUvHulvl265TrZOhGTBUNdHfYHUIj4YTuhebwxoAcuNwMYVIcUmOZ+AJw== X-Received: by 2002:a17:90b:2504:b0:212:def1:623b with SMTP id ns4-20020a17090b250400b00212def1623bmr16483326pjb.47.1667239416866; Mon, 31 Oct 2022 11:03:36 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.03.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:03:35 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 08/15] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Date: Mon, 31 Oct 2022 23:32:10 +0530 Message-Id: <20221031180217.32512-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" goto in error path is useful if the function needs to do cleanup other than returning the error code. But in this driver, goto statements are used for just returning the error code in many places. This really makes it hard to read the code. So let's get rid of those goto statements and just return the error code directly. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 100 +++++++++++++++--------------------- 1 file changed, 41 insertions(+), 59 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8ad1415e10b6..7cd996ac180b 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -110,7 +110,7 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_= host *host) =20 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) { - int err =3D 0; + int err; struct device *dev =3D host->hba->dev; =20 if (host->is_lane_clks_enabled) @@ -119,7 +119,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) err =3D ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", host->rx_l0_sync_clk); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", host->tx_l0_sync_clk); @@ -137,7 +137,8 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) goto disable_rx_l1; =20 host->is_lane_clks_enabled =3D true; - goto out; + + return 0; =20 disable_rx_l1: clk_disable_unprepare(host->rx_l1_sync_clk); @@ -145,7 +146,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) clk_disable_unprepare(host->tx_l0_sync_clk); disable_rx_l0: clk_disable_unprepare(host->rx_l0_sync_clk); -out: + return err; } =20 @@ -160,25 +161,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_ho= st *host) err =3D ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", &host->rx_l0_sync_clk, false); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", &host->tx_l0_sync_clk, false); if (err) - goto out; + return err; =20 /* In case of single lane per direction, don't read lane1 clocks */ if (host->hba->lanes_per_direction > 1) { err =3D ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", &host->rx_l1_sync_clk, false); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", &host->tx_l1_sync_clk, true); } -out: - return err; + + return 0; } =20 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) @@ -241,7 +242,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) =20 if (!host->core_reset) { dev_warn(hba->dev, "%s: reset control not set\n", __func__); - goto out; + return 0; } =20 reenable_intr =3D hba->is_irq_enabled; @@ -252,7 +253,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) if (ret) { dev_err(hba->dev, "%s: core_reset assert failed, err =3D %d\n", __func__, ret); - goto out; + return ret; } =20 /* @@ -274,15 +275,14 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) hba->is_irq_enabled =3D true; } =20 -out: - return ret; + return 0; } =20 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct phy *phy =3D host->generic_phy; - int ret =3D 0; + int ret; bool is_rate_B =3D UFS_QCOM_LIMIT_HS_RATE =3D=3D PA_HS_MODE_B; =20 /* Reset UFS Host Controller and PHY */ @@ -299,7 +299,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) if (ret) { dev_err(hba->dev, "%s: phy init failed, ret =3D %d\n", __func__, ret); - goto out; + return ret; } =20 /* power on phy - start serdes and phy's power and clocks */ @@ -316,7 +316,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) =20 out_disable_phy: phy_exit(phy); -out: + return ret; } =20 @@ -374,7 +374,6 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *h= ba, static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate, bool update_link_startup_timer) { - int ret =3D 0; struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct ufs_clk_info *clki; u32 core_clk_period_in_ns; @@ -409,11 +408,11 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, * Aggregation logic. */ if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) - goto out; + return 0; =20 if (gear =3D=3D 0) { dev_err(hba->dev, "%s: invalid gear =3D %d\n", __func__, gear); - goto out_error; + return -EINVAL; } =20 list_for_each_entry(clki, &hba->clk_list_head, list) { @@ -436,7 +435,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32= gear, } =20 if (ufs_qcom_cap_qunipro(host)) - goto out; + return 0; =20 core_clk_period_in_ns =3D NSEC_PER_SEC / core_clk_rate; core_clk_period_in_ns <<=3D OFFSET_CLK_NS_REG; @@ -451,7 +450,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32= gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rA)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D hs_fr_table_rA[gear-1][1]; } else if (rate =3D=3D PA_HS_MODE_B) { @@ -460,13 +459,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rB)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D hs_fr_table_rB[gear-1][1]; } else { dev_err(hba->dev, "%s: invalid rate =3D %d\n", __func__, rate); - goto out_error; + return -EINVAL; } break; case SLOWAUTO_MODE: @@ -476,14 +475,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(pwm_fr_table)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D pwm_fr_table[gear-1][1]; break; case UNCHANGED: default: dev_err(hba->dev, "%s: invalid mode =3D %d\n", __func__, hs); - goto out_error; + return -EINVAL; } =20 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=3D @@ -507,12 +506,8 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u3= 2 gear, */ mb(); } - goto out; =20 -out_error: - ret =3D -EINVAL; -out: - return ret; + return 0; } =20 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, @@ -527,8 +522,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba = *hba, 0, true)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); - err =3D -EINVAL; - goto out; + return -EINVAL; } =20 if (ufs_qcom_cap_qunipro(host)) @@ -554,7 +548,6 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba = *hba, break; } =20 -out: return err; } =20 @@ -691,8 +684,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, =20 if (!dev_req_params) { pr_err("%s: incoming dev_req_params is NULL\n", __func__); - ret =3D -EINVAL; - goto out; + return -EINVAL; } =20 switch (status) { @@ -720,7 +712,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, if (ret) { pr_err("%s: failed to determine capabilities\n", __func__); - goto out; + return ret; } =20 /* enable the device ref clock before changing to HS mode */ @@ -761,7 +753,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, ret =3D -EINVAL; break; } -out: + return ret; } =20 @@ -773,14 +765,11 @@ static int ufs_qcom_quirk_host_pa_saveconfigtime(stru= ct ufs_hba *hba) err =3D ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), &pa_vs_config_reg1); if (err) - goto out; + return err; =20 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ - err =3D ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), (pa_vs_config_reg1 | (1 << 12))); - -out: - return err; } =20 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) @@ -957,9 +946,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) =20 host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); if (!host) { - err =3D -ENOMEM; dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); - goto out; + return -ENOMEM; } =20 /* Make a two way bind between the qcom host and the hba */ @@ -980,10 +968,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->rcdev.owner =3D dev->driver->owner; host->rcdev.nr_resets =3D 1; err =3D devm_reset_controller_register(dev, &host->rcdev); - if (err) { + if (err) dev_warn(dev, "Failed to register reset controller\n"); - err =3D 0; - } =20 if (!has_acpi_companion(dev)) { host->generic_phy =3D devm_phy_get(dev, "ufsphy"); @@ -1049,17 +1035,16 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->dbg_print_en |=3D UFS_QCOM_DEFAULT_DBG_PRINT_EN; ufs_qcom_get_default_testbus_cfg(host); err =3D ufs_qcom_testbus_config(host); - if (err) { + if (err) + /* Failure is non-fatal */ dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); - err =3D 0; - } =20 - goto out; + return 0; =20 out_variant_clear: ufshcd_set_variant(hba, NULL); -out: + return err; } =20 @@ -1085,7 +1070,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_di= v(struct ufs_hba *hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), &core_clk_ctrl_reg); if (err) - goto out; + return err; =20 core_clk_ctrl_reg &=3D ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; core_clk_ctrl_reg |=3D clk_cycles; @@ -1093,11 +1078,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_d= iv(struct ufs_hba *hba, /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &=3D ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; =20 - err =3D ufshcd_dme_set(hba, + return ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), core_clk_ctrl_reg); -out: - return err; } =20 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) @@ -1180,7 +1163,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, =20 if (err || !dev_req_params) { ufshcd_uic_hibern8_exit(hba); - goto out; + return err; } =20 ufs_qcom_cfg_timers(hba, @@ -1191,8 +1174,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, ufshcd_uic_hibern8_exit(hba); } =20 -out: - return err; + return 0; } =20 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBB85FA3741 for ; Mon, 31 Oct 2022 18:04:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbiJaSE0 (ORCPT ); Mon, 31 Oct 2022 14:04:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbiJaSDx (ORCPT ); Mon, 31 Oct 2022 14:03:53 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFCE913E2E for ; Mon, 31 Oct 2022 11:03:43 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id h2so11365988pgp.4 for ; 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Mon, 31 Oct 2022 11:03:43 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.03.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:03:42 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 09/15] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Date: Mon, 31 Oct 2022 23:32:11 +0530 Message-Id: <20221031180217.32512-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the reset assert and deassert callbacks, the supplied "id" is not used at all and only the hba reset is performed all the time. So there is no reason to use a WARN_ON on the "id". Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney --- drivers/ufs/host/ufs-qcom.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 7cd996ac180b..8bb0f4415f1a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -895,8 +895,6 @@ ufs_qcom_reset_assert(struct reset_controller_dev *rcde= v, unsigned long id) { struct ufs_qcom_host *host =3D rcdev_to_ufs_host(rcdev); =20 - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_assert_reset(host->hba); /* provide 1ms delay to let the reset pulse propagate. */ usleep_range(1000, 1100); @@ -908,8 +906,6 @@ ufs_qcom_reset_deassert(struct reset_controller_dev *rc= dev, unsigned long id) { struct ufs_qcom_host *host =3D rcdev_to_ufs_host(rcdev); =20 - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_deassert_reset(host->hba); =20 /* --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79F0CFA3741 for ; Mon, 31 Oct 2022 18:04:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229663AbiJaSEk (ORCPT ); Mon, 31 Oct 2022 14:04:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229872AbiJaSEA (ORCPT ); Mon, 31 Oct 2022 14:04:00 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DA0C13E85 for ; Mon, 31 Oct 2022 11:03:50 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id r61-20020a17090a43c300b00212f4e9cccdso16605022pjg.5 for ; Mon, 31 Oct 2022 11:03:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=RiMBlIfBxKxj/vF3QFlsYOxRi2XIPOj3IMWWD9vv2naL21WUp4sKZ3OztkVTwLLCr/ QPNdn7tlw4ZYdM4zQ3+HyQUm0LthXMLietdOGhgiRCktIWfWFN5/kkeewGNCMSqDt7tz 60bJcLOsbHR6Hr4YzspMCFETPIF5+BQqGjGgVz5mfIxv4T2zobZmTixyMmJDkJXAxVng 8rreuhH+ONHBFHt83roOzU9NAaBJgpkHFCLJDR1Wa2OusEgTDduDXnhL6GQlm92Xwybu ioNCunM/pOvrD0cZntcmURaYPTMZasNitoJsNGsdCJ6blXxY8sBd/7/JqB+cY02+e1e4 Onvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=xJmWBOrvTf9ZXOKf5ohClJJu0H0itaORpvQ6JuTZm/y69JTGIiwT3r7YEA9PAi7TzZ WVyvCkUjKRX3v1ro0nhKA0Mr1SGS8o/TbJRk6hgX/ilxxmNUw+t7dsFdHGp3Pid9kkyr 6cmohWrR3ZrcbDE4A2+Yr1Zm+/sGMApaBz6BMznzPaZwJUGTHedRwgVrn1AO/NcQ1uqV EnxcDcJ+E/f8npoXscVaiKZ8FoSTaw8t/M4W4dSKI8CK26hUA+yE1lX78ba2T+Pefw9R bSLptcDfyLzajxpS5Jut2DTTFHBL6my4Wq/OBUx+WpnvpPk6rkHrcS9z2IziBkbT4Kq8 eNiw== X-Gm-Message-State: ACrzQf0vVQXGbnVYZ7m4ZhWY0CUth7EHwWpZ6Rt8vd5EiF/ypF8XPwFr I/qBUQJ87grad6RO/KekoW0l X-Google-Smtp-Source: AMsMyM495tr25vJwGEz9GOee1VIPewD2W376fjW8553Y2MxpPs1TKs+xC9JTbyDrYeD0c1kFS3ZDwQ== X-Received: by 2002:a17:90a:72cb:b0:213:fbf0:f5f1 with SMTP id l11-20020a17090a72cb00b00213fbf0f5f1mr2657622pjk.107.1667239430062; Mon, 31 Oct 2022 11:03:50 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.03.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:03:48 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 10/15] scsi: ufs: ufs-qcom: Use bitfields where appropriate Date: Mon, 31 Oct 2022 23:32:12 +0530 Message-Id: <20221031180217.32512-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use bitfield macros where appropriate to simplify the driver. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 44466a395bb5..9d96ac71b27f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -17,12 +17,9 @@ #define DEFAULT_CLK_RATE_HZ 1000000 #define BUS_VECTOR_NAME_LEN 32 =20 -#define UFS_HW_VER_MAJOR_SHFT (28) -#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) -#define UFS_HW_VER_MINOR_SHFT (16) -#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) -#define UFS_HW_VER_STEP_SHFT (0) -#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) +#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) +#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) +#define UFS_HW_VER_STEP_MASK GENMASK(15, 0) =20 /* vendor specific pre-defined parameters */ #define SLOW 1 @@ -76,24 +73,28 @@ enum { #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) =20 /* bit definitions for REG_UFS_CFG1 register */ -#define QUNIPRO_SEL 0x1 -#define UTP_DBG_RAMS_EN 0x20000 +#define QUNIPRO_SEL BIT(0) +#define UFS_PHY_SOFT_RESET BIT(1) +#define UTP_DBG_RAMS_EN BIT(17) #define TEST_BUS_EN BIT(18) #define TEST_BUS_SEL GENMASK(22, 19) #define UFS_REG_TEST_BUS_EN BIT(30) =20 +#define UFS_PHY_RESET_ENABLE 1 +#define UFS_PHY_RESET_DISABLE 0 + /* bit definitions for REG_UFS_CFG2 register */ -#define UAWM_HW_CGC_EN (1 << 0) -#define UARM_HW_CGC_EN (1 << 1) -#define TXUC_HW_CGC_EN (1 << 2) -#define RXUC_HW_CGC_EN (1 << 3) -#define DFC_HW_CGC_EN (1 << 4) -#define TRLUT_HW_CGC_EN (1 << 5) -#define TMRLUT_HW_CGC_EN (1 << 6) -#define OCSC_HW_CGC_EN (1 << 7) +#define UAWM_HW_CGC_EN BIT(0) +#define UARM_HW_CGC_EN BIT(1) +#define TXUC_HW_CGC_EN BIT(2) +#define RXUC_HW_CGC_EN BIT(3) +#define DFC_HW_CGC_EN BIT(4) +#define TRLUT_HW_CGC_EN BIT(5) +#define TMRLUT_HW_CGC_EN BIT(6) +#define OCSC_HW_CGC_EN BIT(7) =20 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ -#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide = */ +#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 b= its wide */ =20 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ @@ -101,17 +102,11 @@ enum { TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) =20 /* bit offset */ -enum { - OFFSET_UFS_PHY_SOFT_RESET =3D 1, - OFFSET_CLK_NS_REG =3D 10, -}; +#define OFFSET_CLK_NS_REG 0xa =20 /* bit masks */ -enum { - MASK_UFS_PHY_SOFT_RESET =3D 0x2, - MASK_TX_SYMBOL_CLK_1US_REG =3D 0x3FF, - MASK_CLK_NS_REG =3D 0xFFFC00, -}; +#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0) +#define MASK_CLK_NS_REG GENMASK(23, 10) =20 /* QCOM UFS debug print bit mask */ #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0) @@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, { u32 ver =3D ufshcd_readl(hba, REG_UFS_HW_VERSION); =20 - *major =3D (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT; - *minor =3D (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT; - *step =3D (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT; + *major =3D FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); + *minor =3D FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); + *step =3D FIELD_GET(UFS_HW_VER_STEP_MASK, ver); }; =20 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_P= HY_RESET_ENABLE), + REG_UFS_CFG1); =20 /* * Make sure assertion of ufs phy reset is written to @@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba= *hba) =20 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_P= HY_RESET_DISABLE), + REG_UFS_CFG1); =20 /* * Make sure de-assertion of ufs phy reset is written to --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9C88FA3741 for ; Mon, 31 Oct 2022 18:04:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230218AbiJaSEd (ORCPT ); Mon, 31 Oct 2022 14:04:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230239AbiJaSEE (ORCPT ); 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Mon, 31 Oct 2022 11:03:55 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 11/15] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Date: Mon, 31 Oct 2022 23:32:13 +0530 Message-Id: <20221031180217.32512-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make use of dev_err_probe() for printing the probe error. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney --- drivers/ufs/host/ufs-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8bb0f4415f1a..38e2ed749d75 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1441,9 +1441,9 @@ static int ufs_qcom_probe(struct platform_device *pde= v) /* Perform generic probe */ err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); if (err) - dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); + return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); =20 - return err; + return 0; } =20 /** --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB2ABFA3741 for ; Mon, 31 Oct 2022 18:05:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229744AbiJaSFF (ORCPT ); Mon, 31 Oct 2022 14:05:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230288AbiJaSEH (ORCPT ); Mon, 31 Oct 2022 14:04:07 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99B4810FC7 for ; Mon, 31 Oct 2022 11:04:05 -0700 (PDT) Received: by mail-pg1-x530.google.com with SMTP id h193so2661293pgc.10 for ; Mon, 31 Oct 2022 11:04:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YE5rC5/HZ6deD3gc3XT/0TjMi23c/Z+tQRwUel8pEh4=; b=ngJIar4cRFhRJ87WFHp+luxDgZu2MaxOeVJXEy03uFeynHfCGlgzi4+nVEms9Rrk/Q ROcU3ieIa5E29iAolL6Yz77bfEMHKLh2mFIhoEnOubAUebbX3Dzmrq3EfuEWPqxXcGAn +rBiHDSlorwin1D7vz7k0tIR9TXt2rDcpAzH0KgK7R9bo7hJdfwl2kDscvhpG21gRei3 12EO1W5NsPVUZGAi3n6ARvNOrJOdZDWH0wgCmOWRsDnRciNmsfVWUCRg64m1ovtl4KFd WqilTAX+Qx8nkQbWp1fEc6ofx7HjegeZT9bzcabe1M2IwGmiYj98lf7yZUYxJEjmd7aJ EkdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YE5rC5/HZ6deD3gc3XT/0TjMi23c/Z+tQRwUel8pEh4=; b=z8ScCIUQN1y5Tv1OKcg6JOv+fPigw3ubLbG7BR3WWlI5Sgvayi5/VaiaHsVQ7PdpFF dQzKy+kEiXti7TyQq21iRi79zxZw+xrk1tvNPek9gbPtMA/dDnJZzQOlCOgzmBUiLThT QctBlD7HetR+Gelema+Zg9cZNb2boehtvSy9b+G3tPCRq1z4iBNu22855LdD9XprEk+H ixx0TcsRJgITWD9b+0Dtr51UNMNzbLkcoTrFYH+eUIjs6IodBxJ2BcumRWo2SdaReRa9 W8ok0UQLCucNy04eO1ubLRBRIVxtb1r8j1/rRcdnckFuMMwfYKEkjCG+wtY99AhScG9m SEEg== X-Gm-Message-State: ACrzQf2wb+nrJTHWz2LcbSP5zIxwyEA7P4PAIOrWnA63D80H3Ufgsij5 z14JwuJLKXtu2bANUSyjpDpg X-Google-Smtp-Source: AMsMyM6yyBG+NNnymIFV2d9Fi+RqjhDyAZ0khdcfg9ZdsJeRcnR/xBL9MobSoFweIhYMbnTUnxEfBA== X-Received: by 2002:a65:68cb:0:b0:460:b552:fbf4 with SMTP id k11-20020a6568cb000000b00460b552fbf4mr13750019pgt.457.1667239445056; Mon, 31 Oct 2022 11:04:05 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.03.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:04:03 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 12/15] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Date: Mon, 31 Oct 2022 23:32:14 +0530 Message-Id: <20221031180217.32512-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On newer UFS revisions, the register at offset 0xD0 is called, REG_UFS_PARAM0. Since the existing register, RETRY_TIMER_REG is not used anywhere, it is safe to use the new name. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney --- drivers/ufs/host/ufs-qcom.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 9d96ac71b27f..7fe928b82753 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -33,7 +33,8 @@ enum { REG_UFS_TX_SYMBOL_CLK_NS_US =3D 0xC4, REG_UFS_LOCAL_PORT_ID_REG =3D 0xC8, REG_UFS_PA_ERR_CODE =3D 0xCC, - REG_UFS_RETRY_TIMER_REG =3D 0xD0, + /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ + REG_UFS_PARAM0 =3D 0xD0, REG_UFS_PA_LINK_STARTUP_TIMER =3D 0xD8, REG_UFS_CFG1 =3D 0xDC, REG_UFS_CFG2 =3D 0xE0, --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C360FA3741 for ; Mon, 31 Oct 2022 18:05:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230236AbiJaSF0 (ORCPT ); Mon, 31 Oct 2022 14:05:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230036AbiJaSEP (ORCPT ); Mon, 31 Oct 2022 14:04:15 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E58ED13DCC for ; Mon, 31 Oct 2022 11:04:11 -0700 (PDT) Received: by mail-pg1-x530.google.com with SMTP id h193so2661499pgc.10 for ; Mon, 31 Oct 2022 11:04:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n09A1w395FEb8CFGE5mj23N+JsxXbyTWGm1Z2TTn0mM=; b=GS8oQJDD8gziLB3T6WUk5TbqFCYkzq8n49LYkyJ+Eq+mA1nyAmGsKjbf6xVjwj8bdy XocrDFfUr1eGr0a31uzd20iFSjCtGOZjOYqAPw8501lWH9xTFfJEg1NFkOStwrEoLsSV iCKPKf5st2Bjc6Aj1BGkVvaHCPyIHVT67bl0HLtbbrZfj4Q6Wy/PKDCbXDx2nX4JQ1y+ o/XkuII+bdxqrvmv9aXP+yIqqKiesoZeR2Z/sci8gJltFT09BT7MS0IAlG9NHcRgNXP9 6POsfU70sxDcG5QvrkFmDTvKpeVBuP6kbg4GQVGAOnJ7+IGUj66m2+o5ePi6C5yJ+h5k dJ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n09A1w395FEb8CFGE5mj23N+JsxXbyTWGm1Z2TTn0mM=; b=jHbJQkRzvIOKFLpDqL7G/4cwYyU5NjlwRqZ/4s+PSN3pl2ujAIAIkZ8u25CtgByZZf gB/4LgkzL66vUNko4BfN4hpyulSWgTvEUQfsxLfAmwySbtfXn+WZKw/MKeV46qceIue0 3Ttg6Wh5cLaGdhvnXH7QIxXcR4vLlOQ9/o/YBMpe0HEeeaDCygABDFPeWaoGT1sF4Tj1 3Ub5Dot7590Y7tUuCCypLKkHj7t/NBrn3XtyFu9z99qar/T7bE/nlGZ6DrjSA7/FRPev LnXHleYOSRm5ZoonowWniDYH6HWX7ACEgdDNdvFNHhNosF8Q6zeiGqKp3T+fmBvLTlfh mjkw== X-Gm-Message-State: ACrzQf22XpzW4cq1ejUgO2D18lwHfmdXfVpVbVsBwC1Sl54lHaGQJjHU +sv6AFtPO092e5BfZbfXfVjO X-Google-Smtp-Source: AMsMyM7iPUdZa99KX1tAK/e56i8Nrgz82UzEeY//bWaCEa59H4AXLhQqaUBJo+M0tlSC0DVJaN4vNQ== X-Received: by 2002:a63:de46:0:b0:46e:c3bd:e47d with SMTP id y6-20020a63de46000000b0046ec3bde47dmr13398495pgi.609.1667239451578; Mon, 31 Oct 2022 11:04:11 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:04:10 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 13/15] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Date: Mon, 31 Oct 2022 23:32:15 +0530 Message-Id: <20221031180217.32512-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the preparation of adding support for new gears, let's move the logic that finds the gear for each platform to a new function. This helps with code readability and also allows the logic to be used in other places of the driver in future. While at it, let's make it clear that this driver only supports symmetric gear setting (hs_tx_gear =3D=3D hs_rx_gear). Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney --- drivers/ufs/host/ufs-qcom.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 38e2ed749d75..c93d2d38b43e 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -278,6 +278,26 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) return 0; } =20 +static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba, u32 hs_gear) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + + if (host->hw_ver.major =3D=3D 0x1) { + /* + * HS-G3 operations may not reliably work on legacy QCOM + * UFS host controller hardware even though capability + * exchange during link startup phase may end up + * negotiating maximum supported gear as G3. + * Hence downgrade the maximum supported gear to HS-G2. + */ + if (hs_gear > UFS_HS_G2) + return UFS_HS_G2; + } + + /* Default is HS-G3 */ + return UFS_HS_G3; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); @@ -692,19 +712,9 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *= hba, ufshcd_init_pwr_dev_param(&ufs_qcom_cap); ufs_qcom_cap.hs_rate =3D UFS_QCOM_LIMIT_HS_RATE; =20 - if (host->hw_ver.major =3D=3D 0x1) { - /* - * HS-G3 operations may not reliably work on legacy QCOM - * UFS host controller hardware even though capability - * exchange during link startup phase may end up - * negotiating maximum supported gear as G3. - * Hence downgrade the maximum supported gear to HS-G2. - */ - if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_tx_gear =3D UFS_HS_G2; - if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_rx_gear =3D UFS_HS_G2; - } + /* This driver only supports symmetic gear setting i.e., hs_tx_gear =3D= =3D hs_rx_gear */ + ufs_qcom_cap.hs_tx_gear =3D ufs_qcom_cap.hs_rx_gear =3D ufs_qcom_get_hs_= gear(hba, + ufs_qcom_cap.hs_tx_gear); =20 ret =3D ufshcd_get_pwr_dev_param(&ufs_qcom_cap, dev_max_params, --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8CA6FA3743 for ; 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Mon, 31 Oct 2022 11:04:17 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 14/15] scsi: ufs: ufs-qcom: Add support for finding HS gear on new UFS versions Date: Mon, 31 Oct 2022 23:32:16 +0530 Message-Id: <20221031180217.32512-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting from UFS controller v4, Qcom supports dual gear mode (i.e., the controller/PHY can be configured to run in two gear speeds). But that requires an agreement between the UFS controller and the UFS device. This commit finds the max gear supported by both controller and device then decides which one to use. UFS controller's max gear can be read from the REG_UFS_PARAM0 register and UFS device's max gear can be read from the "max-device-gear" devicetree property. The UFS PHY also needs to be configured with the decided gear using the phy_set_mode_ext() API. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney --- drivers/ufs/host/ufs-qcom.c | 31 ++++++++++++++++++++++++++++--- drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index c93d2d38b43e..ca60a5b0292b 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -281,6 +281,9 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba, u32 hs_gear) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + struct device *dev =3D hba->dev; + u32 max_device_gear, max_hcd_gear, reg; + int ret; =20 if (host->hw_ver.major =3D=3D 0x1) { /* @@ -292,8 +295,29 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba, u= 32 hs_gear) */ if (hs_gear > UFS_HS_G2) return UFS_HS_G2; + } else if (host->hw_ver.major > 0x3) { + /* + * Starting from UFS controller v4, Qcom supports dual gear mode (i.e., = the + * controller/PHY can be configured to run in two gear speeds). But that + * requires an agreement between the UFS controller and the device. Below + * code tries to find the max gear of both and decides which gear to use. + * + * First get the max gear supported by the UFS device if available. + * If the property is not defined in devicetree, then use the default ge= ar. + */ + ret =3D of_property_read_u32(dev->of_node, "max-device-gear", &max_devic= e_gear); + if (ret) + goto err_out; + + /* Next get the max gear supported by the UFS controller */ + reg =3D ufshcd_readl(hba, REG_UFS_PARAM0); + max_hcd_gear =3D UFS_QCOM_MAX_GEAR(reg); + + /* Now return the minimum of both gears */ + return min(max_device_gear, max_hcd_gear); } =20 +err_out: /* Default is HS-G3 */ return UFS_HS_G3; } @@ -303,7 +327,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct phy *phy =3D host->generic_phy; int ret; - bool is_rate_B =3D UFS_QCOM_LIMIT_HS_RATE =3D=3D PA_HS_MODE_B; + u32 hs_gear; =20 /* Reset UFS Host Controller and PHY */ ret =3D ufs_qcom_host_reset(hba); @@ -311,8 +335,9 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) dev_warn(hba->dev, "%s: host reset returned %d\n", __func__, ret); =20 - if (is_rate_B) - phy_set_mode(phy, PHY_MODE_UFS_HS_B); + /* UFS_HS_G2 is used here since that's the least gear supported by legacy= Qcom platforms */ + hs_gear =3D ufs_qcom_get_hs_gear(hba, UFS_HS_G2); + phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, hs_gear); =20 /* phy initialization - calibrate the phy */ ret =3D phy_init(phy); diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 7fe928b82753..751ded3e3531 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -94,6 +94,10 @@ enum { #define TMRLUT_HW_CGC_EN BIT(6) #define OCSC_HW_CGC_EN BIT(7) =20 +/* bit definitions for REG_UFS_PARAM0 */ +#define MAX_HS_GEAR_MASK GENMASK(6, 4) +#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) + /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 b= its wide */ =20 --=20 2.25.1 From nobody Thu Apr 9 00:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C70B4ECAAA1 for ; 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Mon, 31 Oct 2022 11:04:24 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 15/15] MAINTAINERS: Add myself as the maintainer for Qcom UFS driver Date: Mon, 31 Oct 2022 23:32:17 +0530 Message-Id: <20221031180217.32512-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom UFS driver has been left un-maintained till now. I'd like to step up to maintain the driver and its binding. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf0f18502372..149fd6daf52b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21097,6 +21097,14 @@ L: linux-mediatek@lists.infradead.org (moderated f= or non-subscribers) S: Maintained F: drivers/ufs/host/ufs-mediatek* =20 +UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER QUALCOMM HOOKS +M: Manivannan Sadhasivam +L: linux-arm-msm@vger.kernel.org +L: linux-scsi@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +F: drivers/ufs/host/ufs-qcom.c + UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER RENESAS HOOKS M: Yoshihiro Shimoda L: linux-renesas-soc@vger.kernel.org --=20 2.25.1